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add explicit port mapping support to Verilog testbench generator

This commit is contained in:
tangxifan 2020-05-22 14:40:05 -06:00
parent 6f133bd009
commit bba476fef4
19 changed files with 68 additions and 29 deletions
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2
openfpga/src/base/openfpga_verilog.cpp
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@ -69,6 +69,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_print_formal_verification_top_netlist = cmd.option("print_formal_verification_top_netlist");
CommandOptionId opt_print_preconfig_top_testbench = cmd.option("print_preconfig_top_testbench");
CommandOptionId opt_print_simulation_ini = cmd.option("print_simulation_ini");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -81,6 +82,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench));
options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench));
options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
fpga_verilog_testbench(openfpga_ctx.module_graph(),

3
openfpga/src/base/openfpga_verilog_command.cpp
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@ -89,6 +89,9 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell<Open
CommandOptionId sim_ini_opt = shell_cmd.add_option("print_simulation_ini", false, "Generate a .ini file as an exchangeable file to enable HDL simulations");
shell_cmd.set_option_require_value(sim_ini_opt, openfpga::OPT_STRING);
/* Add an option '--explicit_port_mapping' */
shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");

9
openfpga/src/fpga_verilog/verilog_api.cpp
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@ -183,7 +183,8 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
netlist_name,
formal_verification_top_netlist_file_path);
formal_verification_top_netlist_file_path,
options.explicit_port_mapping());
}
if (true == options.print_preconfig_top_testbench()) {
@ -194,7 +195,8 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
random_top_testbench_file_path,
atom_ctx,
netlist_annotation,
simulation_setting);
simulation_setting,
options.explicit_port_mapping());
}
/* Generate full testbench for verification, including configuration phase and operating phase */
@ -209,7 +211,8 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
netlist_annotation,
netlist_name,
top_testbench_file_path,
simulation_setting);
simulation_setting,
options.explicit_port_mapping());
}
/* Generate exchangeable files which contains simulation settings */

21
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -96,7 +96,8 @@ static
void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
const std::string& reference_verilog_top_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation) {
const VprNetlistAnnotation& netlist_annotation,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
@ -118,7 +119,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
prefix_to_remove,
std::string(BENCHMARK_PORT_POSTFIX),
atom_ctx, netlist_annotation,
true);
explicit_port_mapping);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@ -139,7 +140,8 @@ static
void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
const std::string& circuit_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation) {
const VprNetlistAnnotation& netlist_annotation,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
@ -153,7 +155,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
std::vector<std::string>(),
std::string(FPGA_PORT_POSTFIX),
atom_ctx, netlist_annotation,
true);
explicit_port_mapping);
print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
@ -190,7 +192,8 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
const std::string& verilog_fname,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const SimulationSetting& simulation_parameters) {
const SimulationSetting& simulation_parameters,
const bool& explicit_port_mapping) {
std::string timer_message = std::string("Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by '") + circuit_name.c_str() + std::string("'");
/* Start time count */
@ -214,10 +217,14 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation);
/* Call defined top-level module */
print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx, netlist_annotation);
print_verilog_random_testbench_fpga_instance(fp, circuit_name,
atom_ctx, netlist_annotation,
explicit_port_mapping);
/* Call defined benchmark */
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx, netlist_annotation);
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name,
atom_ctx, netlist_annotation,
explicit_port_mapping);
/* Find clock port to be used */
BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));

3
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
View File

@ -19,7 +19,8 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
const std::string& verilog_fname,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const SimulationSetting& simulation_parameters);
const SimulationSetting& simulation_parameters,
const bool& explicit_port_mapping);
} /* end namespace openfpga */

6
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -385,7 +385,8 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname) {
const std::string& verilog_fname,
const bool& explicit_port_mapping) {
std::string timer_message = std::string("Write pre-configured FPGA top-level Verilog netlist for design '") + circuit_name + std::string("'");
/* Start time count */
@ -414,7 +415,8 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
/* Instanciate FPGA top-level module */
print_verilog_testbench_fpga_instance(fp, module_manager, top_module,
std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME));
std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME),
explicit_port_mapping);
/* Find clock ports in benchmark */
std::vector<std::string> benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);

3
openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
View File

@ -29,7 +29,8 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname);
const std::string& verilog_fname,
const bool& explicit_port_mapping);
} /* end namespace openfpga */

9
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
View File

@ -19,6 +19,7 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
print_formal_verification_top_netlist_ = false;
print_top_testbench_ = false;
simulation_ini_path_.clear();
explicit_port_mapping_ = false;
verbose_output_ = false;
}
@ -53,6 +54,10 @@ std::string VerilogTestbenchOption::simulation_ini_path() const {
return simulation_ini_path_;
}
bool VerilogTestbenchOption::explicit_port_mapping() const {
return explicit_port_mapping_;
}
bool VerilogTestbenchOption::verbose_output() const {
return verbose_output_;
}
@ -97,6 +102,10 @@ void VerilogTestbenchOption::set_print_simulation_ini(const std::string& simulat
simulation_ini_path_ = simulation_ini_path;
}
void VerilogTestbenchOption::set_explicit_port_mapping(const bool& enabled) {
explicit_port_mapping_ = enabled;
}
void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
verbose_output_ = enabled;
}

3
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -29,6 +29,7 @@ class VerilogTestbenchOption {
bool print_top_testbench() const;
bool print_simulation_ini() const;
std::string simulation_ini_path() const;
bool explicit_port_mapping() const;
bool verbose_output() const;
public: /* Public validator */
bool validate() const;
@ -45,6 +46,7 @@ class VerilogTestbenchOption {
void set_print_preconfig_top_testbench(const bool& enabled);
void set_print_top_testbench(const bool& enabled);
void set_print_simulation_ini(const std::string& simulation_ini_path);
void set_explicit_port_mapping(const bool& enabled);
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
std::string output_directory_;
@ -54,6 +56,7 @@ class VerilogTestbenchOption {
bool print_top_testbench_;
/* Print simulation ini is enabled only when the path is not empty */
std::string simulation_ini_path_;
bool explicit_port_mapping_;
bool verbose_output_;
};

6
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -30,7 +30,8 @@ namespace openfpga {
void print_verilog_testbench_fpga_instance(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const std::string& top_instance_name) {
const std::string& top_instance_name,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
@ -43,7 +44,8 @@ void print_verilog_testbench_fpga_instance(std::fstream& fp,
/* Use explicit port mapping for a clean instanciation */
print_verilog_module_instance(fp, module_manager, top_module,
top_instance_name,
port2port_name_map, true);
port2port_name_map,
explicit_port_mapping);
/* Add an empty line as a splitter */
fp << std::endl;

3
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -26,7 +26,8 @@ constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_";
void print_verilog_testbench_fpga_instance(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const std::string& top_instance_name);
const std::string& top_instance_name,
const bool& explicit_port_mapping);
void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& module_name,

14
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -446,7 +446,8 @@ static
void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
const std::string& reference_verilog_top_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation) {
const VprNetlistAnnotation& netlist_annotation,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
@ -468,7 +469,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
prefix_to_remove,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
atom_ctx, netlist_annotation,
true);
explicit_port_mapping);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@ -803,7 +804,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const SimulationSetting& simulation_parameters) {
const SimulationSetting& simulation_parameters,
const bool& explicit_port_mapping) {
std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'");
@ -856,7 +858,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
/* Instanciate FPGA top-level module */
print_verilog_testbench_fpga_instance(fp, module_manager, top_module,
std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME));
std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
explicit_port_mapping);
/* Connect I/Os to benchmark I/Os or constant driver */
print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
@ -870,7 +873,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
print_verilog_top_testbench_benchmark_instance(fp,
circuit_name,
atom_ctx,
netlist_annotation);
netlist_annotation,
explicit_port_mapping);
/* Print tasks used for loading bitstreams */
print_verilog_top_testbench_load_bitstream_task(fp, sram_orgz_type);

3
openfpga/src/fpga_verilog/verilog_top_testbench.h
View File

@ -33,7 +33,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const SimulationSetting& simulation_parameters);
const SimulationSetting& simulation_parameters,
const bool& explicit_port_mapping);
} /* end namespace openfpga */

2
openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
View File

@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

2
openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
View File

@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

2
openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
View File

@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

2
openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
View File

@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

2
openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
View File

@ -45,7 +45,7 @@ build_fabric_bitstream --verbose
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./TESTBENCH --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
write_verilog_testbench --file ./TESTBENCH --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis

2
openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
View File

@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here