riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Test] Update bitstream setting example with mode bit overwriting

This commit is contained in:
tangxifan 2021-03-10 15:34:53 -07:00
parent b42541d84e
commit 7d07f5d8cb
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
View File

@ -1,3 +1,4 @@
<openfpga_bitstream_setting>
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param LUT"/>
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param IN2_IS_CIN" overwrite_mode_bits="true" offset="0"/>
</openfpga_bitstream_setting>