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[Doc] Update documentation about architecture naming rules

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tangxifan 2021-01-12 18:01:24 -07:00
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openfpga_flow/openfpga_arch/README.md
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@ -26,5 +26,6 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
- tree\_mux: If routing multiplexers are built with a tree-like structure
- <feature_size>: The technology node which the delay numbers are extracted from.
- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
- GlobalTile<Int>Clk: How many clocks are defined through global ports from physical tiles. <Int> is the number of clocks
Other features are used in naming should be listed here.