[Doc] Update documentation about architecture naming rules
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@ -26,5 +26,6 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
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- tree\_mux: If routing multiplexers are built with a tree-like structure
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- <feature_size>: The technology node which the delay numbers are extracted from.
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- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
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- GlobalTile<Int>Clk: How many clocks are defined through global ports from physical tiles. <Int> is the number of clocks
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Other features are used in naming should be listed here.
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