Added support for simulation setting file in the task flow
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@ -83,6 +83,8 @@ parser.add_argument('--openfpga_shell_template', type=str,
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help="Sample openfpga shell script")
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parser.add_argument('--openfpga_arch_file', type=str,
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help="Openfpga architecture file for shell")
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parser.add_argument('--openfpga_sim_setting_file', type=str,
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help="Openfpga simulation file for shell")
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parser.add_argument('--yosys_tmpl', type=str,
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help="Alternate yosys template, generates top_module.blif")
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parser.add_argument('--disp', action="store_true",
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@ -683,6 +685,7 @@ def run_openfpga_shell():
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path_variables = script_env_vars["PATH"]
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path_variables["VPR_ARCH_FILE"] = args.arch_file
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path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file
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path_variables["OPENFPGA_SIM_SETTING_FILE"] = args.openfpga_sim_setting_file
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path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif"
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path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act"
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path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \
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@ -355,6 +355,8 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
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task_gc.get("openfpga_shell_template")]
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command += ["--openfpga_arch_file",
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task_gc.get("openfpga_arch_file")]
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command += ["--openfpga_sim_setting_file",
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task_gc.get("openfpga_sim_setting_file")]
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if benchmark_obj.get("activity_file"):
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command += ["--activity_file", benchmark_obj.get("activity_file")]
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@ -16,12 +16,13 @@ verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
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[BENCHMARKS]
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#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
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#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
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#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
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#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
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## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
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@ -39,91 +40,91 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_ti
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#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
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#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
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## Passed
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bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
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#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
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bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
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# bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
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#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
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#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
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#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
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#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
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[SYNTHESIS_PARAM]
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# Benchmark alu4
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# Benchmark alu4
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bench0_top = alu4
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v
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# Benchmark apex2
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# Benchmark apex2
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bench1_top = apex2
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bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act
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bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v
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# Benchmark apex4
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# Benchmark apex4
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bench2_top = apex4
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bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act
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bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v
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# Benchmark bigkey
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# Benchmark bigkey
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bench3_top = bigkey
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bench3_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act
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bench3_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v
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# Benchmark clma
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# Benchmark clma
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bench4_top = clma
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bench4_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act
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bench4_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v
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# Benchmark des
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# Benchmark des
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bench5_top = des
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bench5_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.act
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bench5_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.v
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# Benchmark diffeq
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# Benchmark diffeq
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bench6_top = diffeq
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bench6_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act
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bench6_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v
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# Benchmark dsip
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# Benchmark dsip
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bench7_top = dsip
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bench7_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act
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bench7_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v
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# Benchmark elliptic
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# Benchmark elliptic
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bench8_top = elliptic
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bench8_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act
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bench8_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v
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# Benchmark ex1010
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# Benchmark ex1010
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bench9_top = ex1010
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bench9_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act
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bench9_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v
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# Benchmark ex5p
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# Benchmark ex5p
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bench10_top = ex5p
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bench10_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act
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bench10_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v
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# Benchmark frisc
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# Benchmark frisc
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bench11_top = frisc
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bench11_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act
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bench11_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v
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# Benchmark misex3
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# Benchmark misex3
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bench12_top = misex3
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bench12_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act
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bench12_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v
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# Benchmark pdc
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# Benchmark pdc
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bench13_top = pdc
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bench13_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act
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bench13_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v
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# Benchmark s298
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# Benchmark s298
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bench14_top = s298
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bench14_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act
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bench14_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v
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# Benchmark s38417
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# Benchmark s38417
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bench15_top = s38417
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bench15_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act
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bench15_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v
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# Benchmark s38584
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# Benchmark s38584
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bench16_top = s38584
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bench16_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act
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bench16_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v
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# Benchmark seq
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# Benchmark seq
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bench17_top = seq
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bench17_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act
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bench17_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v
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# Benchmark spla
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# Benchmark spla
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bench18_top = spla
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bench18_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act
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bench18_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v
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# Benchmark tseng
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# Benchmark tseng
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bench19_top = tseng
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bench19_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act
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bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v
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