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Bumping up latest yosys changes related to adder tech mapping

This commit is contained in:
Lalit Sharma 2021-02-03 14:30:06 +05:30
parent f51aaae4a2
commit ebe66dea35
2 changed files with 7 additions and 1 deletions
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6
openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys Normal file
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@ -0,0 +1,6 @@
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -adder -openfpga -top ${TOP_MODULE}

2
yosys

@ -1 +1 @@
Subproject commit 77570b6e0f97f1923ebafd51ebfc9d9224a2f4cf
Subproject commit 1fafc16a257872ac1abbbf14181bbb853f7c8a96