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[Test] Add an example bitstream annotation file

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tangxifan 2021-02-01 16:01:21 -07:00
parent a6354fab7c
commit 280c9620aa
1 changed files with 3 additions and 0 deletions
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3
openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml Normal file
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<bitstream_annotations>
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param LUT"/>
</bitstream_annotations>