diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml
new file mode 100644
index 000000000..efbfcae62
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml
@@ -0,0 +1,3 @@
+<bitstream_annotations>
+  <pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param LUT"/>
+</bitstream_annotations>