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OpenFPGA
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Merge branch 'master' of github.com:lnis-uofu/OpenFPGA

This commit is contained in:
Nachiket Kapre 2021-02-08 21:11:30 -05:00
parent 2344cdcabc 1ce94040da
commit b4185f7e8c
2 changed files with 6 additions and 7 deletions
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4
.github/workflows/basic_reg_test.sh vendored
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@ -116,3 +116,7 @@ run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_
echo -e "Testing yosys flow using custom ys script for running quicklogic device";
run-task quicklogic_tests/flow_test --debug --show_thread_logs
# Repgression test to test multi-user enviroment
cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/
cd /tmp/ && run-task configuration_chain --debug --show_thread_logs

9
openfpga_flow/scripts/run_fpga_flow.py
View File

@ -257,17 +257,12 @@ def main():
logger.info('Running "yosys_vpr" Flow')
run_yosys_with_abc()
# TODO Make it optional if activity file is provided
run_ace2()
run_pro_blif_3arg()
if args.power:
run_ace2()
run_pro_blif_3arg()
run_rewrite_verilog()
if (args.fpga_flow == "vpr_blif"):
collect_files_for_vpr()
# if (args.fpga_flow == "vtr"):
# run_odin2()
# run_abc_vtr()
# if (args.fpga_flow == "vtr_standard"):
# run_abc_for_standarad()
logger.info("Runing OpenFPGA Shell Engine ")
run_openfpga_shell()
if args.end_flow_with_test: