start refactoring the switch block verilog generation
This commit is contained in:
tangxifan
parent
7be83235a0
commit
d7ac7d3649
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@ -19,4 +19,5 @@ end_section "OpenFPGA.build"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd -
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python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow
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python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
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end_section "OpenFPGA.TaskTun"
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@ -38,7 +38,7 @@ vpr_fpga_verilog_print_user_defined_template=
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#vpr_fpga_verilog_print_report_timing_tcl=
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vpr_fpga_verilog_print_sdc_pnr=
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vpr_fpga_verilog_print_sdc_analysis=
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vpr_fpga_x2p_compact_routing_hierarchy=
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#vpr_fpga_x2p_compact_routing_hierarchy=
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end_flow_with_test=
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#[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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@ -8,6 +8,7 @@
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********************************************************************/
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#include "vtr_assert.h"
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#include "sides.h"
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#include "fpga_x2p_naming.h"
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/************************************************
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@ -199,3 +200,85 @@ std::string generate_routing_channel_module_name(const t_rr_type& chan_type,
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return std::string( module_prefix_map[chan_type] + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + std::string("_") );
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}
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/*********************************************************************
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* Generate the port name for a routing track with a given coordinate
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* and port direction
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*********************************************************************/
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std::string generate_routing_track_port_name(const t_rr_type& chan_type,
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const vtr::Point<size_t>& coordinate,
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const size_t& track_id,
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const PORTS& port_direction) {
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/* Channel must be either CHANX or CHANY */
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VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) );
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/* Create a map between chan_type and module_prefix */
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std::map<t_rr_type, std::string> module_prefix_map;
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/* TODO: use a constexpr string to replace the fixed name? */
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module_prefix_map[CHANX] = std::string("chanx");
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module_prefix_map[CHANY] = std::string("chany");
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std::string port_name = module_prefix_map[chan_type];
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port_name += std::string("_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("__"));
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switch (port_direction) {
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case OUT_PORT:
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port_name += std::string("out_");
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break;
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case IN_PORT:
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port_name += std::string("in_");
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of chan_rr_node!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Add the track id to the port name */
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port_name += std::to_string(track_id) + std::string("_");
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return port_name;
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}
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/*********************************************************************
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* Generate the module name for a switch block with a given coordinate
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*********************************************************************/
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std::string generate_switch_block_module_name(const vtr::Point<size_t>& coordinate) {
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return std::string( "sb_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") );
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}
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/*********************************************************************
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* Generate the port name for a Grid
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* TODO: add more comments about why we need different names for
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* top and non-top netlists
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*********************************************************************/
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std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
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const size_t& height,
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const e_side& side,
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const size_t& pin_id,
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const bool& for_top_netlist) {
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if (true == for_top_netlist) {
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std::string port_name = "grid_";
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port_name += std::to_string(coordinate.x());
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port_name += "__";
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port_name += std::to_string(coordinate.y());
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port_name += "__pin_";
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port_name += std::to_string(height);
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port_name += "__";
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port_name += std::to_string(size_t(side));
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port_name += "__";
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port_name += std::to_string(pin_id);
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port_name += "_";
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return port_name;
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}
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/* For non-top netlist */
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VTR_ASSERT( false == for_top_netlist );
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Side side_manager(side);
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std::string port_name = std::string(side_manager.to_string());
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port_name += "_height_";
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port_name += std::to_string(height);
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port_name += "__pin_";
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port_name += std::to_string(pin_id);
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port_name += "_";
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return port_name;
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}
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@ -52,6 +52,19 @@ std::string generate_routing_channel_module_name(const t_rr_type& chan_type,
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const size_t& block_id);
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std::string generate_routing_channel_module_name(const t_rr_type& chan_type,
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const vtr::Point<size_t>& block_id);
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const vtr::Point<size_t>& coordinate);
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std::string generate_routing_track_port_name(const t_rr_type& chan_type,
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const vtr::Point<size_t>& coordinate,
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const size_t& track_id,
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const PORTS& port_direction);
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std::string generate_switch_block_module_name(const vtr::Point<size_t>& coordinate);
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std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
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const size_t& height,
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const e_side& side,
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const size_t& pin_id,
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const bool& for_top_netlist);
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#endif
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@ -0,0 +1,62 @@
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/********************************************************************
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* This file includes most utilized function for rr_block data structures
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*******************************************************************/
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#include <vector>
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#include <algorithm>
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#include "vtr_assert.h"
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#include "vpr_types.h"
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#include "fpga_x2p_types.h"
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#include "rr_blocks_utils.h"
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/*********************************************************************
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* This function will find the global ports required by a Switch Block
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* module. It wil find all the circuit models in the circuit library
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* that may be included in the Switch Block
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* Collect the global ports from the circuit_models and merge with the same name
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********************************************************************/
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std::vector<CircuitPortId> find_switch_block_global_ports(const RRGSB& rr_gsb,
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const CircuitLibrary& circuit_lib,
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const std::vector<t_switch_inf>& switch_lib) {
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std::vector<CircuitModelId> sub_models;
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/* Walk through the OUTPUT nodes at each side of a GSB,
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* get the switch id of incoming edges
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* and get the circuit model linked to the switch id
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*/
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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Side side_manager(side);
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for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
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if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
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continue;
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}
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/* Find the driver switch of the node */
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short driver_switch = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->drive_switches[DEFAULT_SWITCH_ID];
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/* Find the circuit model id of the driver switch */
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VTR_ASSERT( (size_t)driver_switch < switch_lib.size() );
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/* Get the model, and try to add to the sub_model list */
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CircuitModelId switch_circuit_model = switch_lib[driver_switch].circuit_model;
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/* Make sure it is a valid id */
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VTR_ASSERT( CircuitModelId::INVALID() == switch_circuit_model );
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/* Get the model, and try to add to the sub_model list */
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if (sub_models.end() == std::find(sub_models.begin(), sub_models.end(), switch_circuit_model)) {
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/* Not yet in the list, add it */
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sub_models.push_back(switch_circuit_model);
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}
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}
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}
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std::vector<CircuitPortId> global_ports;
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/* Iterate over the model list, and add the global ports*/
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for (const auto& model : sub_models) {
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std::vector<CircuitPortId> temp_global_ports = circuit_lib.model_global_ports(model, true);
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/* Add the temp_global_ports to the list to be returned, make sure we do not have any duplicated ports */
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for (const auto& port_candidate : temp_global_ports) {
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if (global_ports.end() == std::find(global_ports.begin(), global_ports.end(), port_candidate)) {
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/* Not yet in the list, add it */
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global_ports.push_back(port_candidate);
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}
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}
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}
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return global_ports;
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}
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@ -0,0 +1,17 @@
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/********************************************************************
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* Header file for rr_block_utils.cpp
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*******************************************************************/
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#ifndef RR_BLOCKS_UTILS_H
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#define RR_BLOCKS_UTILS_H
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/* Include other header file required by the function declaration */
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#include <vector>
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#include "physical_types.h"
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#include "circuit_library.h"
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#include "rr_blocks.h"
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std::vector<CircuitPortId> find_switch_block_global_ports(const RRGSB& rr_gsb,
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const CircuitLibrary& circuit_lib,
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const std::vector<t_switch_inf>& switch_lib);
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#endif
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@ -280,7 +280,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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/* Dump routing resources: switch blocks, connection blocks and channel tracks */
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print_verilog_routing_resources(module_manager, sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, vpr_setup.RoutingArch,
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print_verilog_routing_resources(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, vpr_setup.RoutingArch,
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num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data,
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vpr_setup.FPGA_SPICE_Opts);
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@ -30,6 +30,7 @@
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/* Include SPICE support headers*/
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#include "linkedlist.h"
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#include "rr_blocks.h"
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#include "rr_blocks_utils.h"
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#include "fpga_x2p_types.h"
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_backannotate_utils.h"
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@ -2121,6 +2122,218 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf
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return;
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}
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/*********************************************************************
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* Generate the Verilog module for a Switch Box.
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* A Switch Box module consists of following ports:
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* 1. Channel Y [x][y] inputs
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* 2. Channel X [x+1][y] inputs
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* 3. Channel Y [x][y-1] outputs
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* 4. Channel X [x][y] outputs
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* 5. Grid[x][y+1] Right side outputs pins
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* 6. Grid[x+1][y+1] Left side output pins
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* 7. Grid[x+1][y+1] Bottom side output pins
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* 8. Grid[x+1][y] Top side output pins
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* 9. Grid[x+1][y] Left side output pins
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* 10. Grid[x][y] Right side output pins
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* 11. Grid[x][y] Top side output pins
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* 12. Grid[x][y+1] Bottom side output pins
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*
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* Location of a Switch Box in FPGA fabric:
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*
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* -------------- --------------
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* | | | |
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* | Grid | ChanY | Grid |
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* | [x][y+1] | [x][y+1] | [x+1][y+1] |
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* | | | |
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* -------------- --------------
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* ----------
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* ChanX | Switch | ChanX
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* [x][y] | Box | [x+1][y]
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* | [x][y] |
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* ----------
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* -------------- --------------
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* | | | |
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* | Grid | ChanY | Grid |
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* | [x][y] | [x][y] | [x+1][y] |
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* | | | |
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* -------------- --------------
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*
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* Switch Block pin location map
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*
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* Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1]
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* right_pins inputs/outputs left_pins
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* | ^ |
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* | | |
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* v v v
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* +-----------------------------------------------+
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* | |
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* Grid[x][y+1] | | Grid[x+1][y+1]
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* bottom_pins---->| |<---- bottom_pins
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* | |
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* ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y]
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* inputs/outputs<--->| |<---> inputs/outputs
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* | |
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* Grid[x][y+1] | | Grid[x+1][y+1]
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* top_pins---->| |<---- top_pins
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* | |
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* +-----------------------------------------------+
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* ^ ^ ^
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* | | |
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* | v |
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* Grid[x][y] ChanY[x][y] Grid[x+1][y]
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* right_pins inputs/outputs left_pins
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*
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*
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********************************************************************/
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static
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void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const std::vector<t_switch_inf>& rr_switches,
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t_sram_orgz_info* cur_sram_orgz_info,
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const std::string& verilog_dir,
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const std::string& subckt_dir,
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const RRGSB& rr_sb,
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const bool& is_explicit_mapping) {
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/* TODO: move this part to another function where we count the conf bits for all the switch blocks !!!*/
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/* Count the number of configuration bits to be consumed by this Switch block */
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int num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, rr_sb);
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/* Count the number of reserved configuration bits to be consumed by this Switch block */
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int num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sram_orgz_info, rr_sb);
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/* Estimate the sram_verilog_model->cnt */
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int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
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int esti_sram_cnt = cur_num_sram + num_conf_bits;
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RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */
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rr_gsb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits);
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rr_gsb.set_sb_conf_bits_lsb(cur_num_sram);
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rr_gsb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1);
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/* Create the netlist */
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix)));
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/* TODO: remove the bak file when the file is ready */
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verilog_fname += ".bak";
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_handler(fp);
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print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]"));
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/* Print preprocessing flags */
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.add_module(generate_switch_block_module_name(gsb_coordinate));
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/* Add ports to the module */
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/* Global ports:
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* In the circuit_library, find all the circuit models that may be included in the Switch Block
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* Collect the global ports from the circuit_models and merge with the same name
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*/
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std::vector<CircuitPortId> global_ports = find_switch_block_global_ports(rr_gsb, circuit_lib, rr_switches);
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for (const auto& port : global_ports) {
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BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
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module_manager.add_port(module_id, module_port, ModuleManager::MODULE_GLOBAL_PORT);
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}
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/* Add routing channel ports at each side of the GSB */
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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Side side_manager(side);
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DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side());
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for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
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vtr::Point<size_t> port_coord(port_coordinator.get_x(), port_coordinator.get_y());
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std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type,
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port_coord, itrack,
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rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack));
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BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */
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switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
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case OUT_PORT:
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module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT);
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break;
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case IN_PORT:
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module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT);
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n",
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__FILE__, __LINE__, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack);
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exit(1);
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}
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}
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/* Dump OPINs of adjacent CLBs */
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for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
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vtr::Point<size_t> port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow,
|
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rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow);
|
||||
std::string port_name = generate_grid_side_port_name(port_coord,
|
||||
rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode),
|
||||
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num);
|
||||
BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */
|
||||
/* Grid outputs are inputs of switch blocks */
|
||||
module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT);
|
||||
}
|
||||
}
|
||||
|
||||
/* Add configuration ports */
|
||||
/* TODO: Reserved sram ports */
|
||||
/*
|
||||
if (0 < rr_sb.get_sb_num_reserved_conf_bits()) {
|
||||
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
|
||||
rr_gsb.get_sb_reserved_conf_bits_lsb(),
|
||||
rr_gsb.get_sb_reserved_conf_bits_msb(),
|
||||
VERILOG_PORT_INPUT);
|
||||
fprintf(fp, ",\n");
|
||||
}
|
||||
*/
|
||||
/* TODO: Normal sram ports */
|
||||
/*
|
||||
dump_verilog_sram_ports(fp, cur_sram_orgz_info,
|
||||
rr_gsb.get_sb_conf_bits_lsb(),
|
||||
rr_gsb.get_sb_conf_bits_msb(),
|
||||
VERILOG_PORT_INPUT);
|
||||
*/
|
||||
/* Dump ports only visible during formal verification*/
|
||||
/*
|
||||
if (0 < rr_sb.get_sb_num_conf_bits()) {
|
||||
fprintf(fp, "\n");
|
||||
fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
|
||||
fprintf(fp, ",\n");
|
||||
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
|
||||
rr_gsb.get_sb_conf_bits_lsb(),
|
||||
rr_gsb.get_sb_conf_bits_msb(),
|
||||
VERILOG_PORT_INPUT, is_explicit_mapping);
|
||||
fprintf(fp, "\n");
|
||||
fprintf(fp, "`endif\n");
|
||||
}
|
||||
fprintf(fp, "); \n");
|
||||
*/
|
||||
|
||||
/* TODO: Local wires for memory configurations */
|
||||
/*
|
||||
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
|
||||
rr_gsb.get_sb_conf_bits_lsb(),
|
||||
rr_gsb.get_sb_conf_bits_msb());
|
||||
*/
|
||||
/* Put an end to the Verilog module */
|
||||
print_verilog_module_end(fp, module_manager.module_name(module_id));
|
||||
|
||||
/* Add an empty line as a splitter */
|
||||
fp << std::endl;
|
||||
|
||||
/* Close file handler */
|
||||
fp.close();
|
||||
|
||||
/* Add fname to the linked list */
|
||||
/*
|
||||
routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str());
|
||||
*/
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Task: Print the subckt of a Switch Box.
|
||||
* A Switch Box subckt consists of following ports:
|
||||
* 1. Channel Y [x][y] inputs
|
||||
|
|
@ -3797,6 +4010,24 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
|
|||
return;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* Generate the port name for a Grid
|
||||
*********************************************************************/
|
||||
std::string generate_grid_side_port_name(const vtr::Point<size_t>& coordinate,
|
||||
const e_side& side,
|
||||
const size_t& pin_id) {
|
||||
/* Output the pins on the side*/
|
||||
int height = get_grid_pin_height(coordinate.x(), coordinate.y(), (int)pin_id);
|
||||
if (1 != grid[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n",
|
||||
__FILE__, __LINE__,
|
||||
coordinate.x(), coordinate.y(), height, convert_side_index_to_string(side), pin_id);
|
||||
exit(1);
|
||||
}
|
||||
return generate_grid_port_name(coordinate, (size_t)height, side, pin_id, true);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* Top-level function:
|
||||
* Build the Verilog modules for global routing architecture
|
||||
|
|
@ -3814,6 +4045,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
|
|||
* unique modules in terms of internal logics
|
||||
*********************************************************************/
|
||||
void print_verilog_routing_resources(ModuleManager& module_manager,
|
||||
const MuxLibrary& mux_lib,
|
||||
t_sram_orgz_info* cur_sram_orgz_info,
|
||||
char* verilog_dir,
|
||||
char* subckt_dir,
|
||||
|
|
@ -3827,6 +4059,13 @@ void print_verilog_routing_resources(ModuleManager& module_manager,
|
|||
|
||||
boolean compact_routing_hierarchy = FPGA_SPICE_Opts.compact_routing_hierarchy;
|
||||
boolean explicit_port_mapping = FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog;
|
||||
|
||||
/* Create a vector of switch infs. TODO: this should be replaced switch objects!!! */
|
||||
std::vector<t_switch_inf> rr_switches;
|
||||
for (short i = 0; i < routing_arch.num_switch; ++i) {
|
||||
rr_switches.push_back(switch_inf[i]);
|
||||
}
|
||||
|
||||
/* Two major tasks:
|
||||
* 1. Generate sub-circuits for Routing Channels
|
||||
* 2. Generate sub-circuits for Switch Boxes
|
||||
|
|
@ -3902,12 +4141,15 @@ void print_verilog_routing_resources(ModuleManager& module_manager,
|
|||
/* Output unique modules */
|
||||
for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
|
||||
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
|
||||
/*
|
||||
dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir,
|
||||
subckt_dir, unique_mirror, explicit_port_mapping);
|
||||
*/
|
||||
dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir,
|
||||
subckt_dir, unique_mirror, explicit_port_mapping);
|
||||
/*
|
||||
print_verilog_routing_switch_box_unique_module(module_manager, arch.spice->circuit_lib, mux_lib,
|
||||
rr_switches,
|
||||
cur_sram_orgz_info, std::string(verilog_dir),
|
||||
std::string(subckt_dir), unique_mirror,
|
||||
explicit_port_mapping);
|
||||
*/
|
||||
}
|
||||
|
||||
/* Restore sram_orgz_info to the base */
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
#define VERILOG_ROUTING_H
|
||||
|
||||
/* Include other header files which are dependency on the function declared below */
|
||||
#include "mux_library.h"
|
||||
#include "module_manager.h"
|
||||
|
||||
void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info,
|
||||
|
|
@ -140,7 +141,12 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
|
|||
bool is_explicit_mapping);
|
||||
|
||||
|
||||
std::string generate_grid_side_port_name(const vtr::Point<size_t>& coordinate,
|
||||
const e_side& side,
|
||||
const size_t& pin_id);
|
||||
|
||||
void print_verilog_routing_resources(ModuleManager& module_manager,
|
||||
const MuxLibrary& mux_lib,
|
||||
t_sram_orgz_info* cur_sram_orgz_info,
|
||||
char* verilog_dir,
|
||||
char* subckt_dir,
|
||||
|
|
|
|||
Loading…
Reference in New Issue