add SRAM verilog for memory bank usage

openfpga_flow/VerilogNetlists/sram.v

@@ -1,3 +1,52 @@
+//-----------------------------------------------------
+// Design Name : sram_blwl
+// File Name   : sram.v
+// Function    : A SRAM cell is is accessible
+//               when wl is enabled
+// Coder       : Xifan TANG
+//-----------------------------------------------------
+module sram_blwl(
+input wl, // Word line control signal
+input bl, // Bit line control signal
+output out, // Data output
+output outb, // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(bl, wl) 
+  begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+    if ((1'b1 == bl)&&(1'b1 == wl)) begin
+      data <= 1'b1;
+    end 
+    //----- case 2: bl = 0, wl = 1, a -> 0
+    if ((1'b0 == bl)&&(1'b1 == wl)) begin
+     data <= 1'b0;
+    end 
+  end
+
+`ifdef ENABLE_SIGNAL_INITIALIZATION
+   initial begin
+     $deposit(data, $random);
+   end
+`endif
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign out = data;
+    assign outb = ~data;
+`else
+    assign out = 1'bZ;
+    assign outb = !out;
+`endif
+
+endmodule
+
+
 //------ Module: sram6T_blwl -----//
 //------ Verilog file: sram.v -----//
 //------ Author: Xifan TANG -----//