riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Architecture] Bring back pin equivalence for no local routing architecture

This commit is contained in:
tangxifan 2020-09-21 22:22:39 -06:00
parent 26f1a5d9ec
commit aa5f5fc7e0
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
View File

@ -54,10 +54,10 @@
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
<input name="I0" num_pins="4" equivalent="none"/>
<input name="I1" num_pins="4" equivalent="none"/>
<input name="I2" num_pins="4" equivalent="none"/>
<input name="I3" num_pins="4" equivalent="none"/>
<input name="I0" num_pins="4" equivalent="full"/>
<input name="I1" num_pins="4" equivalent="full"/>
<input name="I2" num_pins="4" equivalent="full"/>
<input name="I3" num_pins="4" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
@ -211,10 +211,10 @@
However, current annotation engine does not support this
The feature should be enabled after patching
-->
<input name="I0" num_pins="4" equivalent="none"/>
<input name="I1" num_pins="4" equivalent="none"/>
<input name="I2" num_pins="4" equivalent="none"/>
<input name="I3" num_pins="4" equivalent="none"/>
<input name="I0" num_pins="4" equivalent="full"/>
<input name="I1" num_pins="4" equivalent="full"/>
<input name="I2" num_pins="4" equivalent="full"/>
<input name="I3" num_pins="4" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/>
<!-- Describe basic logic element.