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@ -0,0 +1,631 @@
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<!--
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Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
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- 40 nm technology
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- General purpose logic block:
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K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared)
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with optionally registered outputs
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Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
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Carry chain links to vertically adjacent logic blocks
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- Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.
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Height = 6, found on every (8n+2)th column
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- Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.
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Height = 4, found on every (8n+6)th column
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- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
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Details on Modelling:
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The electrical design of the architecture described here is NOT from an
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optimized, SPICED architecture. Instead, we attempt to create a reasonable
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architecture file by using an existing commercial FPGA to approximate the area,
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delay, and power of the underlying components. This is combined with a reasonable 40 nm
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model of wiring and circuit design for low-level routing components, where available.
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The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also
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has wiring electrical parameters that allow the wire lengths and switch patterns to be
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modified and you will still get reasonable delay results for the new architecture.
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The following describes, in detail, how we obtained the various electrical values for this
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architecture.
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Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar
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architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture.
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(n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)
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This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to
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match the overall target (a 40 nm FPGA).
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We obtain delay numbers by measuring delays of routing, soft logic blocks,
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memories, and multipliers from test circuits on a Stratix IV GX device
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(EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4
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wires. Rmetal and Cmetal values for the routing wires were obtained from work done by Charles
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Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and
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take the R and C data from the ITRS roadmap.
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For the general purpose logic block, we assume that the area and delays of the Stratix IV
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crossbar is close enough to the crossbar modelled here. We use 40 inputs and 20 feedback lines in
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the cluster and a full crossbar, leading to 53:1 multiplexers in front of each BLE input.
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Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to
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36:1 multiplexers. We require 60 such multiplexers, while Stratix IV requires 88 for its more
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complex fracturable BLEs + the extra control signals. We justify this rough approximation as follows:
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The Stratix IV crossbar has more inputs (72 vs. 60) and
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outputs (88 vs. 60) than our full crossbar which should increase its area and delay, but the
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Stratix IV crossbar is also 50% sparse (each mux is 36:1 instead of 53:1) which should reduce its
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area and delay. The total number of crossbar switch points is roughly similar between the two
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architectures (3160 for SIV and 3600 for the academic architecture below), so we use the area
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& delay of the Stratix IV crossbar as a rough approximation of our crossbar.
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For LUTs, we include LUT
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delays measured from Stratix IV which is dependant on the input used (ie. some
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LUT inputs are faster than others). The CAD tools at the time of VTR 7 does
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not consider differences in LUT input delays.
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Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.
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Delay obtained by compiling a 256 bit adder (registered inputs and outputs,
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all pins except clock virtual) then measuring the delays in chip-planner,
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sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns,
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inter-block carry delay = 0.327 ns. Given this data, I will approximate
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sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and
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inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has
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overhead that we don't have, I'll approximate the delay of a simpler chain at
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one half what they have. This is very rough, anything from 0.01ns to 0.327ns
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can be justified).
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Logic block area numbers obtained by scaling overall tile area of a 65nm
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Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out
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routing area at a channel width of 300. We use a channel width of 300 because it can route
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all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
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total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
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choosing a width that provides high routability. The architecture can be routed at different channel
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widths, but we estimate the tile size and hence the physical length of routing wires assuming
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a channel width of 300.
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Sanity checks employed:
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1. We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches
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common electrical design.
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Authors: Jason Luu, Jeff Goeders, Vaughn Betz
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-->
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<architecture>
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<!--
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ODIN II specific config begins
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Describes the types of user-specified netlist blocks (in blif, this corresponds to
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".model [type_of_block]") that this architecture supports.
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Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
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already special structures in blif (.names, .input, .output, and .latch)
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that describe them.
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-->
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<models>
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<model name="io">
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<input_ports>
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<port name="outpad"/>
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</input_ports>
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<output_ports>
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<port name="inpad"/>
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</output_ports>
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</model>
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</models>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout auto="1.0" tileable_routing="off"/>
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<spice_settings>
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<parameters>
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<options sim_temp="25" post="off" captab="off" fast="on"/>
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<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
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<cmos abs_variation="0.1" num_sigma="3"/>
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<rram abs_variation="0.1" num_sigma="3"/>
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</monte_carlo>
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<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
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<slew>
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<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
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<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
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</slew>
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<delay>
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<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
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<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
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</delay>
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</measure>
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<stimulate>
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<!--clock op_freq="200e6" sim_slack="0.2" prog_freq="2.5e6"-->
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<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6"> <!--frequency modified to speedup the fpga programing-->
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<rise slew_time="20e-12" slew_type="abs"/>
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<fall slew_time="20e-12" slew_type="abs"/>
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</clock>
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<input>
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<rise slew_time="25e-12" slew_type="abs"/>
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<fall slew_time="25e-12" slew_type="abs"/>
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</input>
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</stimulate>
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</parameters>
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<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="${OPENFPGA_PATH}/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
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<transistors pn_ratio="2" model_ref="M">
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<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
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<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
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<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
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<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
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</transistors>
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<module_circuit_models>
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<circuit_model type="inv_buf" name="INV1X" prefix="INV1X" is_default="1">
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<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf2" prefix="buf2" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="2"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf1" prefix="buf1" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATEX1" prefix="TGATEX1" is_default="1">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<input_buffer exist="off"/>
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<output_buffer exist="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="OR2" prefix="OR2" is_default="1">
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<design_technology type="cmos" topology="OR"/>
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<input_buffer exist="off"/>
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<output_buffer exist="off"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
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<design_technology type="cmos"/>
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<input_buffer exist="off"/>
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<output_buffer exist="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/>
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<!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
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<design_technology type="cmos"/>
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<input_buffer exist="off"/>
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<output_buffer exist="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
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<!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="false">
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<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
|
|
|
|
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<!--mux2to1 subckt_name="mux2to1"/-->
|
|
|
|
|
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
|
|
|
|
<port type="input" prefix="in" size="1"/>
|
|
|
|
|
<port type="sram" prefix="sram" size="1"/>
|
|
|
|
|
<port type="output" prefix="out" size="1"/>
|
|
|
|
|
</circuit_model>
|
|
|
|
|
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="false">
|
|
|
|
|
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
|
|
|
|
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<output_buffer exist="on" circuit_model_name="INV4X"/>
|
|
|
|
|
<!--mux2to1 subckt_name="mux2to1"/-->
|
|
|
|
|
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
|
|
|
|
<port type="input" prefix="in" size="1"/>
|
|
|
|
|
<port type="sram" prefix="sram" size="1"/>
|
|
|
|
|
<port type="output" prefix="out" size="1"/>
|
|
|
|
|
</circuit_model>
|
|
|
|
|
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="1" dump_structural_verilog="false">
|
|
|
|
|
<design_technology type="cmos" structure="one-level" add_const_input="true" const_input_val="1"/>
|
|
|
|
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<output_buffer exist="on" circuit_model_name="INV4X"/>
|
|
|
|
|
<!--mux2to1 subckt_name="mux2to1"/-->
|
|
|
|
|
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
|
|
|
|
<port type="input" prefix="in" size="1"/>
|
|
|
|
|
<port type="sram" prefix="sram" size="1"/>
|
|
|
|
|
<port type="output" prefix="out" size="1"/>
|
|
|
|
|
</circuit_model>
|
|
|
|
|
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
|
|
|
|
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
|
|
|
|
<design_technology type="cmos"/>
|
|
|
|
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
|
|
|
|
<port type="input" prefix="D" size="1"/>
|
|
|
|
|
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
|
|
|
|
|
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
|
|
|
|
|
<port type="output" prefix="Q" size="1"/>
|
|
|
|
|
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
|
|
|
|
|
</circuit_model>
|
|
|
|
|
<circuit_model type="lut" name="unfrac_lut4" prefix="unfrac_lut4" dump_structural_verilog="false">
|
|
|
|
|
<design_technology type="cmos" fracturable_lut="false"/>
|
|
|
|
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<lut_input_inverter exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<lut_intermediate_buffer exist="on" circuit_model_name="buf1" location_map="-1-"/>
|
|
|
|
|
<lut_input_buffer exist="on" circuit_model_name="buf2"/>
|
|
|
|
|
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
|
|
|
|
<port type="input" prefix="in" size="4"/>
|
|
|
|
|
<port type="output" prefix="out" size="1" lut_output_mask="0"/>
|
|
|
|
|
<port type="sram" prefix="sram" size="16"/>
|
|
|
|
|
</circuit_model>
|
|
|
|
|
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
|
|
|
|
<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
|
|
|
|
|
<design_technology type="cmos"/>
|
|
|
|
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
|
|
|
|
<port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
|
|
|
|
<!-- <port type="input" prefix="pSet" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> -->
|
|
|
|
|
<port type="input" prefix="D" size="1"/>
|
|
|
|
|
<port type="output" prefix="Q" size="1"/>
|
|
|
|
|
<port type="output" prefix="Qb" size="1"/>
|
|
|
|
|
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
|
|
|
|
</circuit_model>
|
|
|
|
|
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
|
|
|
|
|
<design_technology type="cmos"/>
|
|
|
|
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
|
|
|
|
<port type="inout" prefix="pad" size="1"/>
|
|
|
|
|
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
|
|
|
|
<!--port type="sram" prefix="enb" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="0"/-->
|
|
|
|
|
<port type="input" prefix="outpad" size="1"/>
|
|
|
|
|
<!-- <port type="input" prefix="zin" size="1" is_global="true" default_val="0" /> -->
|
|
|
|
|
<port type="output" prefix="inpad" size="1"/>
|
|
|
|
|
</circuit_model>
|
|
|
|
|
<!-- Hard logic definition for heterogenous blocks -->
|
|
|
|
|
<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="false" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
|
|
|
|
|
<design_technology type="cmos"/>
|
|
|
|
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<port type="input" prefix="a" size="1"/>
|
|
|
|
|
<port type="input" prefix="b" size="1"/>
|
|
|
|
|
<port type="input" prefix="cin" size="1"/>
|
|
|
|
|
<port type="output" prefix="sumout" size="1"/>
|
|
|
|
|
<port type="output" prefix="cout" size="1"/>
|
|
|
|
|
</circuit_model>
|
|
|
|
|
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
|
|
|
|
|
<design_technology type="cmos"/>
|
|
|
|
|
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
|
|
|
|
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
|
|
|
|
<port type="input" prefix="in" size="1"/>
|
|
|
|
|
<port type="output" prefix="out" size="2"/>
|
|
|
|
|
</circuit_model>
|
|
|
|
|
|
|
|
|
|
</module_circuit_models>
|
|
|
|
|
</spice_settings>
|
|
|
|
|
<device>
|
|
|
|
|
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
|
|
|
|
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
|
|
|
|
|
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
|
|
|
|
|
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
|
|
|
|
|
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
|
|
|
|
|
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
|
|
|
|
|
lined up with Stratix IV.
|
|
|
|
|
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
|
|
|
|
|
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
|
|
|
|
|
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
|
|
|
|
|
by 2.5x when looking up in Jeff's tables.
|
|
|
|
|
The delay values are lined up with Stratix IV, which has an architecture similar to this
|
|
|
|
|
proposed FPGA, and which is also 40 nm
|
|
|
|
|
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
|
|
|
|
|
4x minimum drive strength buffer. -->
|
|
|
|
|
|
|
|
|
|
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
|
|
|
|
|
<timing C_ipin_cblock="596e-18" T_ipin_cblock="77.93e-12"/>
|
|
|
|
|
|
|
|
|
|
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
|
|
|
|
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
|
|
|
|
-->
|
|
|
|
|
<area grid_logic_tile_area="0"/>
|
|
|
|
|
<sram area="6">
|
|
|
|
|
<verilog organization="scan-chain" circuit_model_name="sc_dff_compact"/>
|
|
|
|
|
<!--verilog organization="memory-bank" circuit_model_name="sram6T_blwl"/-->
|
|
|
|
|
<spice organization="standalone" circuit_model_name="sram6T" />
|
|
|
|
|
</sram>
|
|
|
|
|
<chan_width_distr>
|
|
|
|
|
<io width="1.000000"/>
|
|
|
|
|
<x distr="uniform" peak="1.000000"/>
|
|
|
|
|
<y distr="uniform" peak="1.000000"/>
|
|
|
|
|
</chan_width_distr>
|
|
|
|
|
<switch_block type="wilton" fs="3"/>
|
|
|
|
|
</device>
|
|
|
|
|
|
|
|
|
|
<cblocks>
|
|
|
|
|
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
|
|
|
|
|
</switch>
|
|
|
|
|
</cblocks>
|
|
|
|
|
<switchlist>
|
|
|
|
|
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
|
|
|
|
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
|
|
|
|
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
|
|
|
|
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
|
|
|
|
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
|
|
|
|
|
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
|
|
|
|
|
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
|
|
|
|
|
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
|
|
|
|
|
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
|
|
|
|
|
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
|
|
|
|
|
2.5x when looking up in Jeff's tables.
|
|
|
|
|
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
|
|
|
|
|
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
|
|
|
|
|
<switch type="mux" name="sb_mux_L16" R="0" Cin="0" Cout="" Tdel="1.3e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
|
|
|
|
|
</switch>
|
|
|
|
|
<switch type="mux" name="sb_mux_L4" R="0" Cin="0" Cout="" Tdel="0.72e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
|
|
|
|
|
</switch>
|
|
|
|
|
<switch type="mux" name="sb_mux_L2" R="115" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
|
|
|
|
|
</switch>
|
|
|
|
|
<switch type="mux" name="sb_mux_L1" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
|
|
|
|
|
</switch>
|
|
|
|
|
</switchlist>
|
|
|
|
|
<segmentlist>
|
|
|
|
|
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
|
|
|
|
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
|
|
|
|
|
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
|
|
|
|
|
<segment freq="0.13" length="16" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
|
|
|
|
|
<mux name="sb_mux_L16"/>
|
|
|
|
|
<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
|
|
|
|
|
<cb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</cb>
|
|
|
|
|
</segment>
|
|
|
|
|
<segment freq="0.87" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
|
|
|
|
|
<mux name="sb_mux_L4"/>
|
|
|
|
|
<sb type="pattern">1 1 1 1 1</sb>
|
|
|
|
|
<cb type="pattern">1 1 1 1</cb>
|
|
|
|
|
</segment>
|
|
|
|
|
</segmentlist>
|
|
|
|
|
<!--switch_segment_patterns>
|
|
|
|
|
<pattern type="unbuf_sb" seg_length="1" seg_type="unidir" pattern_length="2">
|
|
|
|
|
<unbuf_mux name="1"/>
|
|
|
|
|
<sb type ="pattern">0 1</sb>
|
|
|
|
|
</pattern>
|
|
|
|
|
</switch_segment_patterns-->
|
|
|
|
|
|
|
|
|
|
<complexblocklist>
|
|
|
|
|
|
|
|
|
|
<!-- Define I/O pads begin -->
|
|
|
|
|
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
|
|
|
|
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
|
|
|
|
<pb_type name="io" capacity="2" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
|
|
|
|
|
<input name="outpad" num_pins="1"/>
|
|
|
|
|
<output name="inpad" num_pins="1"/>
|
|
|
|
|
|
|
|
|
|
<!-- physical design description -->
|
|
|
|
|
<mode name="io_phy" disabled_in_packing="true">
|
|
|
|
|
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
|
|
|
|
|
<input name="outpad" num_pins="1"/>
|
|
|
|
|
<output name="inpad" num_pins="1"/>
|
|
|
|
|
</pb_type>
|
|
|
|
|
<interconnect>
|
|
|
|
|
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
|
|
|
|
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
|
|
|
|
</direct>
|
|
|
|
|
<direct name="outpad" input="io.outpad" output="iopad.outpad">
|
|
|
|
|
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
|
|
|
|
</direct>
|
|
|
|
|
</interconnect>
|
|
|
|
|
</mode>
|
|
|
|
|
|
|
|
|
|
<!-- IOs can operate as either inputs or outputs.§
|
|
|
|
|
Delays below come from Ian Kuon. They are small, so they should be interpreted as
|
|
|
|
|
the delays to and from registers in the I/O (and generally I/Os are registered
|
|
|
|
|
today and that is when you timing analyze them.
|
|
|
|
|
-->
|
|
|
|
|
<mode name="inpad">
|
|
|
|
|
<pb_type name="inpad" blif_model=".input" num_pb="1" physical_pb_type_name="iopad" mode_bits="1">
|
|
|
|
|
<output name="inpad" num_pins="1" physical_mode_pin="inpad"/>
|
|
|
|
|
</pb_type>
|
|
|
|
|
<interconnect>
|
|
|
|
|
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
|
|
|
|
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
|
|
|
|
</direct>
|
|
|
|
|
</interconnect>
|
|
|
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1" physical_pb_type_name="iopad" mode_bits="0">
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<input name="outpad" num_pins="1" physical_mode_pin="outpad"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
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<fc default_in_type="frac" default_in_val="0.30" default_out_type="frac" default_out_val="0.10"/>
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<!-- IOs go on the periphery of the FPGA, for consistency,
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make it physically equivalent on all sides so that only one definition of I/Os is needed.
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If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
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-->
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad</loc>
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<loc side="top">io.outpad io.inpad</loc>
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<loc side="right">io.outpad io.inpad</loc>
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<loc side="bottom">io.outpad io.inpad</loc>
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</pinlocations>
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<!-- Place I/Os on the sides of the FPGA -->
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<gridlocations>
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<loc type="perimeter" priority="10"/>
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</gridlocations>
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<power method="ignore"/>
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</pb_type>
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<!-- Define I/O pads ends -->
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<!-- Define general purpose logic block (CLB) begin -->
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<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
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area is 60 L^2 yields a tile area of 84375 MWTAs.
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Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
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This means that only 37% of our area is in the general routing, and 63% is inside the logic
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block. Note that the crossbar / local interconnect is considered part of the logic block
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area in this analysis. That is a lower proportion of of routing area than most academics
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assume, but note that the total routing area really includes the crossbar, which would push
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routing area up significantly, we estimate into the ~70% range.
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-->
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<pb_type name="clb" area="11388">
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<input name="I" num_pins="12" equivalent="true"/>
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<output name="O" num_pins="4" equivalent="false"/>
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<clock name="clk" num_pins="1"/>
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<!-- Describe fracturable logic element.
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Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
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The outputs of the fracturable logic element can be optionally registered
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-->
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<pb_type name="fle" num_pb="4">
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<input name="in" num_pins="4"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="logic" num_pb="1">
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<input name="in" num_pins="4"/>
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<output name="out" num_pins="1"/>
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<pb_type name="lut4" blif_model=".names" num_pb="1" circuit_model_name="unfrac_lut4" class="lut">
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<input name="in" num_pins="4" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
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202e-12
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202e-12
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202e-12
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202e-12
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</delay_matrix>
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</pb_type>
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<interconnect>
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<direct name="direct_lut_in" input="logic.in[3:0]" output="lut4.in[3:0]"/>
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<direct name="direct_lut_out" input="lut4.out" output="logic.out"/>
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</interconnect>
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</pb_type>
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<pb_type name="ff_phy" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<complete name="direct_clk" input="fle.clk" output="ff_phy.clk"/>
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<direct name="direct_in" input="fle.in[3:0]" output="logic.in[3:0]"/>
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<direct name="direct_frac_out1" input="logic.out" output="ff_phy.D"/>
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<mux name="mux_out" input="ff_phy.Q logic.out" output="fle.out">
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<!-- We use a full crossbar to get logical equivalence at inputs of CLB
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The delays below come from Stratix IV. the delay through a connection block
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|
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
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delay on the connection block input mux (modeled by Ian Kuon), so the remaining
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delay within the crossbar is 95 ps.
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|
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
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|
Since all our outputs LUT outputs go to a BLE output, and have a delay of
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|
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
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|
to get the part that should be marked on the crossbar. -->
|
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|
|
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" circuit_model_name="mux_2level">
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|
<delay_constant max="90.2e-12" in_port="clb.I" out_port="fle[3:0].in" />
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|
|
<delay_constant max="70.2e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
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|
</complete>
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|
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
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|
</complete>
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|
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
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|
|
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
|
|
|
|
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
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|
|
|
naive specification).
|
|
|
|
|
-->
|
|
|
|
|
<direct name="clbouts1" input="fle[3:0].out" output="clb.O[3:0]"/>
|
|
|
|
|
</interconnect>
|
|
|
|
|
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|
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|
|
<fc default_in_type="frac" default_in_val="0.1" default_out_type="frac" default_out_val="0.10">
|
|
|
|
|
</fc>
|
|
|
|
|
|
|
|
|
|
<pinlocations pattern="custom">
|
|
|
|
|
<loc side="top">clb.clk </loc>
|
|
|
|
|
<loc side="right">clb.I[5:0] clb.O[1:0]</loc>
|
|
|
|
|
<loc side="bottom">clb.I[11:6] clb.O[3:2]</loc>
|
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|
|
<loc side="left"></loc>
|
|
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|
|
</pinlocations>
|
|
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|
|
<gridlocations>
|
|
|
|
|
<loc type="fill" priority="1"/>
|
|
|
|
|
</gridlocations>
|
|
|
|
|
</pb_type>
|
|
|
|
|
<!-- Define general purpose logic block (CLB) ends -->
|
|
|
|
|
</complexblocklist>
|
|
|
|
|
<power>
|
|
|
|
|
<local_interconnect C_wire="2.5e-10"/>
|
|
|
|
|
<mux_transistor_size mux_transistor_size="3"/>
|
|
|
|
|
<FF_size FF_size="4"/>
|
|
|
|
|
<LUT_transistor_size LUT_transistor_size="4"/>
|
|
|
|
|
</power>
|
|
|
|
|
<clocks>
|
|
|
|
|
<clock buffer_size="auto" C_wire="2.5e-10"/>
|
|
|
|
|
</clocks>
|
|
|
|
|
</architecture>
|
tangxifan