From 5cb3717433b775fc58228a1380f98c423e158ff1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 28 Oct 2019 15:57:17 -0600
Subject: [PATCH] add single mode test case to regression test. debugging now

---
 ...m_chain_FC_behavioral_verilog_template.xml | 631 ++++++++++++++++++
 .../test_modes/k4_N4/K4N4_test_modes.act      |  16 +
 .../test_modes/k4_N4/K4N4_test_modes.blif     |  40 ++
 .../test_modes/k4_N4/K4N4_test_modes.v        |  54 ++
 .../k6_N10/K6N10_test_modes.act}              |   0
 .../k6_N10/K6N10_test_modes.blif}             |   0
 .../k6_N10/K6N10_test_modes.v}                |   0
 .../tasks/blif_vpr_flow/config/task.conf      |   6 +-
 .../tasks/explicit_verilog/config/task.conf   |   6 +-
 .../tasks/single_mode/config/task.conf        |  58 ++
 .../tasks/tileable_routing/config/task.conf   |   6 +-
 11 files changed, 808 insertions(+), 9 deletions(-)
 create mode 100644 openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
 create mode 100644 openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act
 create mode 100644 openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif
 create mode 100644 openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v
 rename openfpga_flow/benchmarks/{Test_Modes/test_modes.act => test_modes/k6_N10/K6N10_test_modes.act} (100%)
 rename openfpga_flow/benchmarks/{Test_Modes/test_modes.blif => test_modes/k6_N10/K6N10_test_modes.blif} (100%)
 rename openfpga_flow/benchmarks/{Test_Modes/test_modes.v => test_modes/k6_N10/K6N10_test_modes.v} (100%)
 create mode 100644 openfpga_flow/tasks/single_mode/config/task.conf

diff --git a/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml b/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
new file mode 100644
index 000000000..29f091673
--- /dev/null
+++ b/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
@@ -0,0 +1,631 @@
+<!--
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block:
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared)
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable
+  architecture file by using an existing commercial FPGA to approximate the area,
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture.
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks,
+  memories, and multipliers from test circuits on a Stratix IV GX device
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and
+  take the R and C data from the ITRS roadmap.
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV
+  crossbar is close enough to the crossbar modelled here.  We use 40 inputs and 20 feedback lines in
+  the cluster and a full crossbar, leading to 53:1 multiplexers in front of each BLE input.
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to
+  36:1 multiplexers.  We require 60 such multiplexers, while Stratix IV requires 88 for its more
+  complex fracturable BLEs + the extra control signals. We justify this rough approximation as follows:
+  The Stratix IV crossbar has more inputs (72 vs. 60) and
+  outputs (88 vs. 60) than our full crossbar which should increase its area and delay, but the
+  Stratix IV crossbar is also 50% sparse (each mux is 36:1 instead of 53:1) which should reduce its
+  area and delay.  The total number of crossbar switch points is roughly similar between the two
+  architectures (3160 for SIV and 3600 for the academic architecture below), so we use the area
+  & delay of the Stratix IV crossbar as a rough approximation of our crossbar.
+
+  For LUTs, we include LUT
+  delays measured from Stratix IV which is dependant on the input used (ie. some
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs,
+  all pins except clock virtual) then measuring the delays in chip-planner,
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns,
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has
+  overhead that we don't have, I'll approximate the delay of a simpler chain at
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out
+  routing area at a channel width of 300. We use a channel width of 300 because it can route
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+
+
+<architecture>
+
+  <!--
+       ODIN II specific config begins
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
+       already special structures in blif (.names, .input, .output, and .latch)
+       that describe them.
+  -->
+  <models>
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+  </models>
+  <!-- ODIN II specific config ends -->
+
+  <!-- Physical descriptions begin -->
+  <layout auto="1.0" tileable_routing="off"/>
+  <spice_settings>
+    <parameters>
+      <options sim_temp="25" post="off" captab="off" fast="on"/>
+      <monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
+        <cmos abs_variation="0.1" num_sigma="3"/>
+        <rram abs_variation="0.1" num_sigma="3"/>
+      </monte_carlo>
+      <measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
+        <slew>
+          <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+          <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+        </slew>
+        <delay>
+          <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+          <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+        </delay>
+      </measure>
+      <stimulate>
+        <!--clock op_freq="200e6" sim_slack="0.2" prog_freq="2.5e6"-->
+        <clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6">          <!--frequency modified to speedup the fpga programing-->
+          <rise slew_time="20e-12" slew_type="abs"/>
+          <fall slew_time="20e-12" slew_type="abs"/>
+        </clock>
+        <input>
+          <rise slew_time="25e-12" slew_type="abs"/>
+          <fall slew_time="25e-12" slew_type="abs"/>
+        </input>
+      </stimulate>
+    </parameters>
+    <tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="${OPENFPGA_PATH}/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
+    <transistors pn_ratio="2" model_ref="M">
+      <nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
+      <pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
+      <io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
+      <io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
+    </transistors>
+    <module_circuit_models>
+      <circuit_model type="inv_buf" name="INV1X" prefix="INV1X" is_default="1">
+        <design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <delay_matrix type="rise" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+        <delay_matrix type="fall" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <delay_matrix type="rise" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+        <delay_matrix type="fall" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <delay_matrix type="rise" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+        <delay_matrix type="fall" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <delay_matrix type="rise" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+        <delay_matrix type="fall" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="buf2" prefix="buf2" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="2"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <delay_matrix type="rise" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+        <delay_matrix type="fall" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="buf1" prefix="buf1" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="off"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <delay_matrix type="rise" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+        <delay_matrix type="fall" in_port="in" out_port="out">
+          10e-12
+        </delay_matrix>
+      </circuit_model>
+      <circuit_model type="pass_gate" name="TGATEX1" prefix="TGATEX1" is_default="1">
+        <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+        <input_buffer exist="off"/>
+        <output_buffer exist="off"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="input" prefix="sel" size="1"/>
+        <port type="input" prefix="selb" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+          10e-12 5e-12 5e-12
+        </delay_matrix>
+        <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+          10e-12 5e-12 5e-12
+        </delay_matrix>
+      </circuit_model>
+      <circuit_model type="gate" name="OR2" prefix="OR2" is_default="1">
+        <design_technology type="cmos" topology="OR"/>
+        <input_buffer exist="off"/>
+        <output_buffer exist="off"/>
+        <port type="input" prefix="a" size="1"/>
+        <port type="input" prefix="b" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <delay_matrix type="rise" in_port="a b" out_port="out">
+          10e-12 10e-12
+        </delay_matrix>
+        <delay_matrix type="fall" in_port="a b" out_port="out">
+          10e-12 10e-12
+        </delay_matrix>
+      </circuit_model>
+      <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
+        <design_technology type="cmos"/>
+        <input_buffer exist="off"/>
+        <output_buffer exist="off"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/>
+        <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+      </circuit_model>
+      <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
+        <design_technology type="cmos"/>
+        <input_buffer exist="off"/>
+        <output_buffer exist="off"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+        <wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
+        <!-- model_type could be T, res_val cap_val should be defined -->
+      </circuit_model>
+      <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="false">
+        <design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
+        <input_buffer exist="on" circuit_model_name="INV1X"/>
+        <output_buffer exist="on" circuit_model_name="INV1X"/>
+        <!--mux2to1 subckt_name="mux2to1"/-->
+        <pass_gate_logic circuit_model_name="TGATEX1"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="sram" prefix="sram" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+      </circuit_model>
+      <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="false">
+        <design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
+        <input_buffer exist="on" circuit_model_name="INV1X"/>
+        <output_buffer exist="on" circuit_model_name="INV4X"/>
+        <!--mux2to1 subckt_name="mux2to1"/-->
+        <pass_gate_logic circuit_model_name="TGATEX1"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="sram" prefix="sram" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+      </circuit_model>
+      <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="1" dump_structural_verilog="false">
+        <design_technology type="cmos" structure="one-level" add_const_input="true" const_input_val="1"/>
+        <input_buffer exist="on" circuit_model_name="INV1X"/>
+        <output_buffer exist="on" circuit_model_name="INV4X"/>
+        <!--mux2to1 subckt_name="mux2to1"/-->
+        <pass_gate_logic circuit_model_name="TGATEX1"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="sram" prefix="sram" size="1"/>
+        <port type="output" prefix="out" size="1"/>
+      </circuit_model>
+      <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+      <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+        <design_technology type="cmos"/>
+        <input_buffer exist="on" circuit_model_name="INV1X"/>
+        <output_buffer exist="on" circuit_model_name="INV1X"/>
+        <pass_gate_logic circuit_model_name="TGATEX1"/>
+        <port type="input" prefix="D" size="1"/>
+        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+        <port type="output" prefix="Q" size="1"/>
+        <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+      </circuit_model>
+      <circuit_model type="lut" name="unfrac_lut4" prefix="unfrac_lut4" dump_structural_verilog="false">
+        <design_technology type="cmos" fracturable_lut="false"/>
+        <input_buffer exist="on" circuit_model_name="INV1X"/>
+        <output_buffer exist="on" circuit_model_name="INV1X"/>
+        <lut_input_inverter exist="on" circuit_model_name="INV1X"/>
+        <lut_intermediate_buffer exist="on" circuit_model_name="buf1" location_map="-1-"/>
+        <lut_input_buffer exist="on" circuit_model_name="buf2"/>
+        <pass_gate_logic circuit_model_name="TGATEX1"/>
+        <port type="input" prefix="in" size="4"/>
+        <port type="output" prefix="out" size="1" lut_output_mask="0"/>
+        <port type="sram" prefix="sram" size="16"/>
+      </circuit_model>
+      <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+      <circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+        <design_technology type="cmos"/>
+        <input_buffer exist="on" circuit_model_name="INV1X"/>
+        <output_buffer exist="on" circuit_model_name="INV1X"/>
+        <pass_gate_logic circuit_model_name="TGATEX1"/>
+        <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+        <!-- <port type="input" prefix="pSet" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> -->
+        <port type="input" prefix="D" size="1"/>
+        <port type="output" prefix="Q" size="1"/>
+        <port type="output" prefix="Qb" size="1"/>
+        <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+      </circuit_model>
+      <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+        <design_technology type="cmos"/>
+        <input_buffer exist="on" circuit_model_name="INV1X"/>
+        <output_buffer exist="on" circuit_model_name="INV1X"/>
+        <pass_gate_logic circuit_model_name="TGATEX1"/>
+        <port type="inout" prefix="pad" size="1"/>
+        <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+        <!--port type="sram" prefix="enb" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="0"/-->
+        <port type="input" prefix="outpad" size="1"/>
+        <!-- <port type="input" prefix="zin" size="1" is_global="true" default_val="0" /> -->
+        <port type="output" prefix="inpad" size="1"/>
+      </circuit_model>
+      <!-- Hard logic definition for heterogenous blocks -->
+      <circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="false" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+        <design_technology type="cmos"/>
+        <input_buffer exist="on" circuit_model_name="INV1X"/>
+        <output_buffer exist="on" circuit_model_name="INV1X"/>
+        <port type="input" prefix="a" size="1"/>
+        <port type="input" prefix="b" size="1"/>
+        <port type="input" prefix="cin" size="1"/>
+        <port type="output" prefix="sumout" size="1"/>
+        <port type="output" prefix="cout" size="1"/>
+      </circuit_model>
+      <circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
+        <design_technology type="cmos"/>
+        <input_buffer exist="on" circuit_model_name="INV1X"/>
+        <output_buffer exist="on" circuit_model_name="INV1X"/>
+        <pass_gate_logic circuit_model_name="TGATEX1"/>
+        <port type="input" prefix="in" size="1"/>
+        <port type="output" prefix="out" size="2"/>
+      </circuit_model>
+
+    </module_circuit_models>
+  </spice_settings>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV.
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
+    <timing C_ipin_cblock="596e-18" T_ipin_cblock="77.93e-12"/>
+
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <sram area="6">
+      <verilog organization="scan-chain" circuit_model_name="sc_dff_compact"/>
+      <!--verilog organization="memory-bank" circuit_model_name="sram6T_blwl"/-->
+      <spice organization="standalone" circuit_model_name="sram6T" />
+    </sram>
+    <chan_width_distr>
+      <io width="1.000000"/>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+  </device>
+
+  <cblocks>
+    <switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
+    </switch>
+  </cblocks>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="sb_mux_L16" R="0" Cin="0" Cout="" Tdel="1.3e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
+    </switch>
+    <switch type="mux" name="sb_mux_L4" R="0" Cin="0" Cout="" Tdel="0.72e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
+    </switch>
+    <switch type="mux" name="sb_mux_L2" R="115" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
+    </switch>
+    <switch type="mux" name="sb_mux_L1" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
+    </switch>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment freq="0.13" length="16" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
+      <mux name="sb_mux_L16"/>
+      <sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</cb>
+    </segment>
+    <segment freq="0.87" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
+      <mux name="sb_mux_L4"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <!--switch_segment_patterns>
+    <pattern type="unbuf_sb" seg_length="1" seg_type="unidir" pattern_length="2">
+      <unbuf_mux name="1"/>
+      <sb type ="pattern">0 1</sb>
+    </pattern>
+  </switch_segment_patterns-->
+
+  <complexblocklist>
+
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io" capacity="2" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- physical design description -->
+      <mode name="io_phy" disabled_in_packing="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.§
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1" physical_pb_type_name="iopad" mode_bits="1">
+          <output name="inpad" num_pins="1" physical_mode_pin="inpad"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1" physical_pb_type_name="iopad" mode_bits="0">
+          <input name="outpad" num_pins="1" physical_mode_pin="outpad"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <fc default_in_type="frac" default_in_val="0.30" default_out_type="frac" default_out_val="0.10"/>
+
+      <!-- IOs go on the periphery of the FPGA, for consistency,
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+
+      <!-- Place I/Os on the sides of the FPGA -->
+      <gridlocations>
+        <loc type="perimeter" priority="10"/>
+      </gridlocations>
+
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+
+
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range.
+	   -->
+    <pb_type name="clb" area="11388">
+      <input name="I" num_pins="12" equivalent="true"/>
+      <output name="O" num_pins="4" equivalent="false"/>
+      <clock name="clk" num_pins="1"/>
+
+      <!-- Describe fracturable logic element.
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <output name="out" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+          <pb_type name="logic" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <pb_type name="lut4" blif_model=".names" num_pb="1" circuit_model_name="unfrac_lut4" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+                <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                </delay_matrix>
+            </pb_type>
+            <interconnect>
+              <direct name="direct_lut_in" input="logic.in[3:0]" output="lut4.in[3:0]"/>
+              <direct name="direct_lut_out" input="lut4.out" output="logic.out"/>
+            </interconnect>
+          </pb_type>
+          <pb_type name="ff_phy" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
+            <input name="D" num_pins="1" port_class="D"/>
+            <output name="Q" num_pins="1" port_class="Q"/>
+            <clock name="clk" num_pins="1" port_class="clock"/>
+            <T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
+            <T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
+          </pb_type>
+          <interconnect>
+            <complete name="direct_clk" input="fle.clk" output="ff_phy.clk"/>
+            <direct name="direct_in" input="fle.in[3:0]" output="logic.in[3:0]"/>
+            <direct name="direct_frac_out1" input="logic.out" output="ff_phy.D"/>
+            <mux name="mux_out" input="ff_phy.Q logic.out" output="fle.out">
+            </mux>
+          </interconnect>
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps.
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" circuit_model_name="mux_2level">
+          <delay_constant max="90.2e-12" in_port="clb.I" out_port="fle[3:0].in" />
+          <delay_constant max="70.2e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out" output="clb.O[3:0]"/>
+      </interconnect>
+
+      <fc default_in_type="frac" default_in_val="0.1" default_out_type="frac" default_out_val="0.10">
+      </fc>
+
+      <pinlocations pattern="custom">
+        <loc side="top">clb.clk </loc>
+        <loc side="right">clb.I[5:0] clb.O[1:0]</loc>
+        <loc side="bottom">clb.I[11:6] clb.O[3:2]</loc>
+        <loc side="left"></loc>
+      </pinlocations>
+      <gridlocations>
+        <loc type="fill" priority="1"/>
+      </gridlocations>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+  <power>
+    <local_interconnect C_wire="2.5e-10"/>
+    <mux_transistor_size mux_transistor_size="3"/>
+    <FF_size FF_size="4"/>
+    <LUT_transistor_size LUT_transistor_size="4"/>
+  </power>
+  <clocks>
+    <clock buffer_size="auto" C_wire="2.5e-10"/>
+  </clocks>
+</architecture>
diff --git a/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act
new file mode 100644
index 000000000..159a6071f
--- /dev/null
+++ b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act
@@ -0,0 +1,16 @@
+clk       0.5 0.2    
+a         0.5 0.2    
+b         0.5 0.2     
+c         0.5 0.2     
+XOR       0.5 0.2     
+XNOR      0.5 0.2    
+OR        0.5 0.2    
+NOR       0.5 0.2     
+AND       0.5 0.2     
+NAND      0.5 0.2        
+XOR_sync  0.5 0.2     
+XNOR_sync 0.5 0.2    
+OR_sync   0.5 0.2    
+NOR_sync  0.5 0.2     
+AND_sync  0.5 0.2     
+NAND_sync 0.5 0.2  
diff --git a/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif
new file mode 100644
index 000000000..d74125339
--- /dev/null
+++ b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif
@@ -0,0 +1,40 @@
+.model K4n4_test
+.inputs clk a b c
+.outputs XOR XNOR AND NAND OR NOR XOR_sync XNOR_sync AND_sync NAND_sync OR_sync NOR_sync
+
+.names a b c XOR
+100 1
+010 1
+001 1
+111 1
+
+.names a b c XNOR
+011 1
+101 1
+110 1
+000 1
+
+.names a b c AND
+111 1
+
+.names a b c NAND
+0-- 1
+-0- 1
+--0 1
+
+.names a b c OR
+1-- 1
+-1- 1
+--1 1
+
+.names a b c NOR
+000 1
+
+.latch   XOR     XOR_sync  re  clk  0
+.latch   XNOR    XNOR_sync re  clk  0
+.latch   OR      OR_sync   re  clk  0
+.latch   NOR     NOR_sync  re  clk  0
+.latch   AND     AND_sync  re  clk  0
+.latch   NAND    NAND_sync re  clk  0
+
+.end
diff --git a/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v
new file mode 100644
index 000000000..5826ed571
--- /dev/null
+++ b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v
@@ -0,0 +1,54 @@
+`timescale 1ns / 1ps
+
+module K4n4_test (
+	clk,
+	a,
+	b,
+	c,
+	XOR,
+	XNOR,
+	AND,
+	NAND,
+	OR,
+	NOR,
+	XOR_sync,
+	XNOR_sync,
+	AND_sync,
+	NAND_sync,
+	OR_sync,
+	NOR_sync );
+
+	input  wire clk;
+	input  wire a;
+	input  wire b;
+	input  wire c;
+	output wire XOR;
+	output wire XNOR;
+	output wire AND;
+	output wire NAND;
+	output wire OR;
+	output wire NOR;
+	output reg  XOR_sync;
+	output reg  XNOR_sync;
+	output reg  AND_sync;
+	output reg  NAND_sync;
+	output reg  OR_sync;
+	output reg  NOR_sync;
+
+	assign XOR = a ^ b ^ c;
+	assign XNOR = !XOR;
+	assign OR = a || b || c;
+	assign NOR = !( a || b || c);
+	assign AND = a && b && c;
+	assign NAND = !(a && b && c);
+
+	always @(posedge clk) begin
+		XOR_sync = XOR;
+		XNOR_sync = XNOR;
+		OR_sync = OR;
+		NOR_sync = NOR;
+		AND_sync = AND;
+		NAND_sync = NAND;
+	end
+
+endmodule
diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.act b/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act
similarity index 100%
rename from openfpga_flow/benchmarks/Test_Modes/test_modes.act
rename to openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act
diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.blif b/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif
similarity index 100%
rename from openfpga_flow/benchmarks/Test_Modes/test_modes.blif
rename to openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif
diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.v b/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v
similarity index 100%
rename from openfpga_flow/benchmarks/Test_Modes/test_modes.v
rename to openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v
diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf
index c54ce8403..7cadfce2c 100644
--- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf
+++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf
@@ -25,12 +25,12 @@ arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO
 #arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = test_modes
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v
 bench0_chan_width = 300
 
 #[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/explicit_verilog/config/task.conf b/openfpga_flow/tasks/explicit_verilog/config/task.conf
index 0634a32c5..2a640bfae 100644
--- a/openfpga_flow/tasks/explicit_verilog/config/task.conf
+++ b/openfpga_flow/tasks/explicit_verilog/config/task.conf
@@ -19,12 +19,12 @@ arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tem
 #arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = test_modes
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT]
diff --git a/openfpga_flow/tasks/single_mode/config/task.conf b/openfpga_flow/tasks/single_mode/config/task.conf
new file mode 100644
index 000000000..f7086ab77
--- /dev/null
+++ b/openfpga_flow/tasks/single_mode/config/task.conf
@@ -0,0 +1,58 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = K4n4_test
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v
+bench0_chan_width = 100
+
+#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
+#fix_route_chan_width=300
+#vpr_fpga_verilog_include_icarus_simulator=
+#vpr_fpga_verilog_formal_verification_top_netlist=
+#vpr_fpga_verilog_include_timing=
+#vpr_fpga_verilog_include_signal_init=
+#vpr_fpga_verilog_print_autocheck_top_testbench=
+#vpr_fpga_bitstream_generator=
+#vpr_fpga_verilog_print_user_defined_template=
+#vpr_fpga_verilog_print_report_timing_tcl=
+#vpr_fpga_verilog_print_sdc_pnr=
+#vpr_fpga_verilog_print_sdc_analysis=
+#vpr_fpga_x2p_compact_routing_hierarchy=
+#end_flow_with_test=
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0]
+min_route_chan_width=1.3
+vpr_fpga_verilog_include_icarus_simulator=
+vpr_fpga_verilog_formal_verification_top_netlist=
+vpr_fpga_verilog_include_timing=
+vpr_fpga_verilog_include_signal_init=
+vpr_fpga_verilog_print_autocheck_top_testbench=
+vpr_fpga_bitstream_generator=
+vpr_fpga_verilog_print_user_defined_template=
+vpr_fpga_verilog_print_report_timing_tcl=
+vpr_fpga_verilog_print_sdc_pnr=
+vpr_fpga_verilog_print_sdc_analysis=
+#vpr_fpga_verilog_explicit_mapping=
+#vpr_fpga_x2p_compact_routing_hierarchy=
+end_flow_with_test=
diff --git a/openfpga_flow/tasks/tileable_routing/config/task.conf b/openfpga_flow/tasks/tileable_routing/config/task.conf
index 3a7f092a6..860a9ba32 100644
--- a/openfpga_flow/tasks/tileable_routing/config/task.conf
+++ b/openfpga_flow/tasks/tileable_routing/config/task.conf
@@ -18,12 +18,12 @@ fpga_flow=vpr_blif
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = test_modes
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]