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[Arch] Add dummy timing info to adder_lut4 and carry_follower model

This commit is contained in:
tangxifan 2021-02-02 15:49:43 -07:00
parent dc320182b0
commit 021520783b
1 changed files with 9 additions and 4 deletions
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13
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -35,7 +35,7 @@
</model>
<model name="adder_lut4">
<input_ports>
<port name="in"/>
<port name="in" combinational_sink_ports="lut2_out lut4_out"/>
</input_ports>
<output_ports>
<port name="lut2_out"/>
@ -54,9 +54,9 @@
</model>
<model name="carry_follower">
<input_ports>
<port name="a"/>
<port name="b"/>
<port name="cin"/>
<port name="a" combinational_sink_ports="cout"/>
<port name="b" combinational_sink_ports="cout"/>
<port name="cin" combinational_sink_ports="cout"/>
</input_ports>
<output_ports>
<port name="cout"/>
@ -500,12 +500,17 @@
<input name="in" num_pins="4"/>
<output name="lut2_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/>
<delay_constant max="0.3e-9" in_port="adder_lut4.in" out_port="adder_lut4.lut2_out"/>
<delay_constant max="0.3e-9" in_port="adder_lut4.in" out_port="adder_lut4.lut4_out"/>
</pb_type>
<pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1">
<input name="a" num_pins="1"/>
<input name="b" num_pins="1"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/>
<delay_constant max="0.3e-9" in_port="carry_follower.a" out_port="carry_follower.cout"/>
<delay_constant max="0.3e-9" in_port="carry_follower.b" out_port="carry_follower.cout"/>
<delay_constant max="0.3e-9" in_port="carry_follower.cin" out_port="carry_follower.cout"/>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">