BugFix : Relative path for refrence benchmark fixed

openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga

@@ -40,8 +40,8 @@ build_fabric_bitstream --verbose
 write_fabric_verilog --file ./SRC \
   --explicit_port_mapping \
   --include_timing \
-  --include_signal_init 
-  #--support_icarus_simulator 
+  --include_signal_init
+  #--support_icarus_simulator
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists
@@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC \
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ./${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here

openfpga_flow/scripts/run_modelsim.py

@@ -182,7 +182,7 @@ def create_tcl_script(files):
         with open(IncludeFileResolved, "w") as fpw:
             with open(IncludeFile, "r") as fp:
                 for eachline in fp.readlines():
-                    eachline = eachline.replace("./SRC", "../../../SRC/")
+                    eachline = eachline.replace("\"./", "\"../../../")
                     fpw.write(eachline)
         # Modify the variables in config file here
         config["TOP_TB"] = os.path.splitext(config["TOP_TB"])[0]