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bug fixed for std cell MUX2 architecture and add the case to regression tests

This commit is contained in:
tangxifan 2019-11-06 16:06:47 -07:00
parent 09eb373a6e
commit 4ea5756be6
4 changed files with 1094 additions and 7 deletions
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53
openfpga_flow/VerilogNetlists/mux2.v Normal file
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@ -0,0 +1,53 @@
//-----------------------------------------------------
// Design Name : MUX2
// File Name : mux2.v
// Function : Standard cell (static gate) implementation
// of 2-input multiplexers
// Coder : Xifan Tang
//-----------------------------------------------------
module MUX2(
input A, // Data input 0
input B, // Data input 1
input S0, // Select port
output Y // Data output
);
assign Y = S0 ? B : A;
// Note:
// MUX2 appears will appear in LUTs, routing multiplexers,
// being a component in combinational loops
// To help convergence in simulation
// i.e., to avoid the X (undetermined) signals,
// the following timing constraints and signal initialization
// has to be added!
`ifdef ENABLE_TIMING
// ------ BEGIN Pin-to-pin Timing constraints -----
specify
(A => Y) = (0.001, 0.001);
(B => Y) = (0.001, 0.001);
(S0 => Y) = (0.001, 0.001);
endspecify
// ------ END Pin-to-pin Timing constraints -----
`endif
`ifdef ENABLE_SIGNAL_INITIALIZATION
// ------ BEGIN driver initialization -----
initial begin
`ifdef ENABLE_FORMAL_VERIFICATION
$deposit(A, 1'b0);
$deposit(B, 1'b0);
$deposit(S0, 1'b0);
`else
$deposit(A, $random);
$deposit(B, $random);
$deposit(S0, $random);
`endif
end
// ------ END driver initialization -----
`endif
endmodule

1030
openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml Normal file
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13
openfpga_flow/tasks/multi_mode/config/task.conf
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@ -15,12 +15,13 @@ timeout_each_job = 20*60
fpga_flow=vpr_blif
[ARCHITECTURES]
arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml
arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml
arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml
arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml
arch6=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml
arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml
arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml
arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml
arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml
arch6=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp
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@ -1192,7 +1192,10 @@ void generate_verilog_mux_module(ModuleManager& module_manager,
ModuleId mux_module = module_manager.find_module(module_name);
VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
write_verilog_module_to_file(fp, module_manager, mux_module,
use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model));
( use_explicit_port_map
|| circuit_lib.dump_explicit_port_map(mux_model)
|| circuit_lib.dump_explicit_port_map(circuit_lib.pass_gate_logic_model(mux_model)) )
);
/* Add an empty line as a splitter */
fp << std::endl;
break;