no need for dff*, but need tap_buf4

openfpga_flow/openfpga_cell_library/verilog/buf4.v

@@ -4,6 +4,13 @@ output [0:0] const0;
 assign const0[0] = 1'b0;
 endmodule
 
+// ----- Verilog module for const0 -----
+module const1(const1);
+output [0:0] const1;
+assign const1[0] = 1'b1;
+endmodule
+
+
 // ----- Verilog module for buf4 -----
 module buf4(in,
             out);