[Architecture] Bug fix in DFF Verilog HDL

openfpga_flow/VerilogNetlists/dff.v

@@ -17,7 +17,7 @@ module DFF (
 reg q_reg;
 
 //-------------Code Starts Here---------
-always @ ( posedge CK) 
+always @ (posedge CK) begin 
   q_reg <= D;
 end