[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock

openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v

@@ -0,0 +1,60 @@
+/* Generated by Yosys 0.9+2406 (git sha1 a0606e09, gcc 8.4.0 -fPIC -Os) */
+
+module counter4bit_2clock(clk0, rst0, clk1, rst1, \q0[0] , \q0[1] , \q0[2] , \q0[3] , \q1[0] , \q1[1] , \q1[2] , \q1[3] );
+  wire _00_;
+  wire _01_;
+  input clk0;
+  input clk1;
+  wire n26;
+  wire n30;
+  wire n34;
+  wire n38;
+  wire n42;
+  wire n46;
+  wire n50;
+  wire n54;
+  output \q0[0] ;
+  reg \q0[0] ;
+  output \q0[1] ;
+  reg \q0[1] ;
+  output \q0[2] ;
+  reg \q0[2] ;
+  output \q0[3] ;
+  reg \q0[3] ;
+  output \q1[0] ;
+  reg \q1[0] ;
+  output \q1[1] ;
+  reg \q1[1] ;
+  output \q1[2] ;
+  reg \q1[2] ;
+  output \q1[3] ;
+  reg \q1[3] ;
+  input rst0;
+  input rst1;
+  always @(posedge clk1)
+      \q1[0]  <= n26;
+  always @(posedge clk1)
+      \q1[1]  <= n30;
+  always @(posedge clk1)
+      \q1[2]  <= n34;
+  always @(posedge clk1)
+      \q1[3]  <= n38;
+  always @(posedge clk1)
+      \q0[0]  <= n42;
+  always @(posedge clk1)
+      \q0[1]  <= n46;
+  always @(posedge clk1)
+      \q0[2]  <= n50;
+  always @(posedge clk1)
+      \q0[3]  <= n54;
+  assign n38 = 4'h1 >> { _00_, rst1 };
+  assign _00_ = 16'h807f >> { \q1[3] , \q1[1] , \q1[0] , \q1[2]  };
+  assign n42 = 4'h1 >> { \q0[0] , rst0 };
+  assign n46 = 8'h14 >> { \q0[0] , \q0[1] , rst0 };
+  assign n50 = 16'h0708 >> { \q0[2] , rst0, \q0[0] , \q0[1]  };
+  assign n54 = 4'h1 >> { _01_, rst0 };
+  assign _01_ = 16'h807f >> { \q0[3] , \q0[0] , \q0[1] , \q0[2]  };
+  assign n26 = 4'h1 >> { rst1, \q1[0]  };
+  assign n30 = 8'h14 >> { \q1[1] , \q1[0] , rst1 };
+  assign n34 = 16'h0708 >> { \q1[2] , rst1, \q1[1] , \q1[0]  };
+endmodule