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[Test] Update test case to use eblif file

This commit is contained in:
tangxifan 2021-02-02 09:33:41 -07:00
parent 39e6f62d91
commit 5e2847bc41
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf
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@ -26,7 +26,7 @@ external_fabric_key_file=
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif
[SYNTHESIS_PARAM]
bench0_top = and2