From 5e2847bc41937f7f76e4280bd23c758b3d94c8b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 09:33:41 -0700 Subject: [PATCH] [Test] Update test case to use eblif file --- .../tasks/fpga_verilog/adder/soft_adder/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index 8a94c37ea..93f0c2d6a 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -26,7 +26,7 @@ external_fabric_key_file= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif [SYNTHESIS_PARAM] bench0_top = and2