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add explicit port mapping support in testbenches; remove dangling ports in benchmarks

This commit is contained in:
tangxifan 2019-11-02 23:03:47 -06:00
parent 05a830de1b
commit dc241e6c03
5 changed files with 48 additions and 21 deletions
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1
openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act
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@ -13,7 +13,6 @@ i_11_ 0.495600 0.504600
i_12_ 0.502800 0.507600
i_13_ 0.494600 0.500600
i_14_ 0.504800 0.502800
i_15_ 0.487600 0.495200
i_16_ 0.504000 0.505200
i_17_ 0.497400 0.512600
i_18_ 0.502200 0.502200

2
openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
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@ -1,7 +1,7 @@
# Benchmark "apex2" written by ABC on Tue Mar 12 09:34:21 2019
.model apex2
.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \
i_13_ i_14_ i_15_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ \
i_13_ i_14_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ \
i_25_ i_26_ i_27_ i_28_ i_29_ i_30_ i_31_ i_32_ i_33_ i_34_ i_35_ i_36_ \
i_37_ i_38_
.outputs o_0_ o_1_ o_2_

3
openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v
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@ -1,13 +1,12 @@
/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */
module apex2(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_, i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, o_0_, o_1_, o_2_);
module apex2(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, i_14_, i_16_, i_17_, i_18_, i_19_, i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, o_0_, o_1_, o_2_);
input i_0_;
input i_10_;
input i_11_;
input i_12_;
input i_13_;
input i_14_;
input i_15_;
input i_16_;
input i_17_;
input i_18_;

23
openfpga_flow/tasks/mcnc_big20/config/task.conf
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@ -15,13 +15,16 @@ timeout_each_job = 20*60
fpga_flow=vpr_blif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
#arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
# Pass
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
# Fail, due to port does not match, i_15_ is dangling
#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
# To be tested
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
@ -34,8 +37,10 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif # Pass
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif # Multi-mode support fails to repack
# Pass
#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
# Multi-mode support fails to repack
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
@ -147,10 +152,10 @@ vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_verilog_print_report_timing_tcl=
#vpr_fpga_verilog_print_sdc_pnr=
#vpr_fpga_verilog_print_sdc_analysis=
vpr_fpga_verilog_explicit_mapping=
vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=
#end_flow_with_test=

40
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp
View File

@ -182,8 +182,11 @@ static
void print_verilog_random_testbench_instance(std::fstream& fp,
const std::string& module_name,
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& output_port_postfix,
const std::vector<t_logical_block>& L_logical_blocks) {
const std::vector<t_logical_block>& L_logical_blocks,
const bool& use_explicit_port_map) {
/* Validate the file stream */
check_file_handler(fp);
@ -202,10 +205,24 @@ void print_verilog_random_testbench_instance(std::fstream& fp,
}
/* Input port follows the logical block name while output port requires a special postfix */
if (VPACK_INPAD == lb.type){
fp << "\t\t" << std::string(lb.name);
fp << "\t\t";
if (true == use_explicit_port_map) {
fp << "." << std::string(lb.name) << module_input_port_postfix << "(";
}
fp << std::string(lb.name);
if (true == use_explicit_port_map) {
fp << ")";
}
} else {
VTR_ASSERT_SAFE(VPACK_OUTPAD == lb.type);
fp << "\t\t" << std::string(lb.name) << output_port_postfix;
fp << "\t\t";
if (true == use_explicit_port_map) {
fp << "." << std::string(lb.name) << module_output_port_postfix << "(";
}
fp << std::string(lb.name) << output_port_postfix;
if (true == use_explicit_port_map) {
fp << ")";
}
}
/* Update the counter */
port_counter++;
@ -213,8 +230,6 @@ void print_verilog_random_testbench_instance(std::fstream& fp,
fp << "\t);" << std::endl;
}
/********************************************************************
* Instanciate the input benchmark module
*******************************************************************/
@ -230,9 +245,15 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
/* Do NOT use explicit port mapping here:
* VPR added a prefix of "out_" to the output ports of input benchmark
*/
print_verilog_random_testbench_instance(fp, reference_verilog_top_name,
std::string(BENCHMARK_INSTANCE_NAME),
std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks);
std::string(),
std::string(),
std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks,
false);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@ -389,10 +410,13 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
print_verilog_comment(fp, std::string("----- FPGA fabric instanciation -------"));
/* Always use explicit port mapping */
print_verilog_random_testbench_instance(fp, std::string(circuit_name + std::string(formal_verification_top_postfix)),
std::string(FPGA_INSTANCE_NAME),
std::string(FPGA_PORT_POSTFIX), L_logical_blocks);
std::string(formal_verification_top_module_port_postfix),
std::string(formal_verification_top_module_port_postfix),
std::string(FPGA_PORT_POSTFIX), L_logical_blocks,
true);
print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));