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[Arch] Introduce new XML syntax for global port in tile annotation

This commit is contained in:
tangxifan 2021-01-09 15:48:42 -07:00
parent cde26597ed
commit a14a56772a
1 changed files with 3 additions and 1 deletions
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4
openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
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@ -169,7 +169,9 @@
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotations>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
<global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk"/>
</global_port>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->