From a14a56772ae97fa9f7e0fa36e943bb679745ac3f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 9 Jan 2021 15:48:42 -0700
Subject: [PATCH] [Arch] Introduce new XML syntax for global port in tile
 annotation

---
 .../openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml    | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
index d3f4baf4b..67b9dd360 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
@@ -169,7 +169,9 @@
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
   <tile_annotations>
-    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
+    <global_port name="clk" is_clock="true" default_val="0">
+      <tile name="clb" port="clk"/>
+    </global_port>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->