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[Arch] Fine tune example arch

This commit is contained in:
tangxifan 2020-11-10 14:38:47 -07:00
parent 6fbdbe68ae
commit 75ce4b5e25
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/openfpga_arch/k4_N4_40nm_local_clock_cc_openfpga.xml
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@ -168,9 +168,9 @@
<routing_segment>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotation>
<tile_annotations>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
</tile_annotation>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>