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[Test] Bug fix for test case configuration

This commit is contained in:
tangxifan 2021-02-01 11:19:47 -07:00
parent a80acfb547
commit 940dce469a
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf
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@ -17,7 +17,7 @@ fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
external_fabric_key_file=