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[Flow] Add comments for the design constraint file

This commit is contained in:
tangxifan 2021-01-16 15:34:01 -07:00
parent 6ab0f71896
commit 9154cfdeec
1 changed files with 9 additions and 0 deletions
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9
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml
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@ -1,5 +1,14 @@
<repack_pin_constraints>
<!-- For a given .blif file, we want to assign
- the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
- the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
and ensure no signals could be mapped to
- the clk[2] port of all the clb tiles available in the FPGA fabric
- the clk[3] port of all the clb tiles available in the FPGA fabric
-->
<pin_constraint tile="clb" name="clk[0]" net="clk0"/>
<pin_constraint tile="clb" name="clk[1]" net="clk1"/>
<pin_constraint tile="clb" name="clk[2]" net="OPEN"/>
<pin_constraint tile="clb" name="clk[3]" net="OPEN"/>
</repack_pin_constraints>