[Flow] Add comments for the design constraint file
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<repack_pin_constraints>
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<!-- For a given .blif file, we want to assign
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- the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
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- the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
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and ensure no signals could be mapped to
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- the clk[2] port of all the clb tiles available in the FPGA fabric
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- the clk[3] port of all the clb tiles available in the FPGA fabric
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-->
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<pin_constraint tile="clb" name="clk[0]" net="clk0"/>
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<pin_constraint tile="clb" name="clk[1]" net="clk1"/>
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<pin_constraint tile="clb" name="clk[2]" net="OPEN"/>
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<pin_constraint tile="clb" name="clk[3]" net="OPEN"/>
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</repack_pin_constraints>
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