[Architecture] Enrich SRAM Verilog HDL for flexible set/reset support
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tangxifan
parent
70a8c6dc29
commit
6bb30ab33c
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@ -42,27 +42,32 @@ output outb // Data output
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endmodule
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module sram_blwl_set(
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input set, // Word line control signal
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input wl, // Word line control signal
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input bl, // Bit line control signal
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output out, // Data output
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output outb // Data output
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//-----------------------------------------------------
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// Function : A SRAM cell with
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// - an active-high set
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// - a write-enable
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//-----------------------------------------------------
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module SRAMS(
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input SET, // active-high set signal
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input WE, // Word line control signal as write enable
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input D, // Bit line control signal as data input
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output Q, // Data output
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output QN // Data output
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);
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//----- local variable need to be registered
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reg data;
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//----- when wl is enabled, we can read in data from bl
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always @(bl or wl)
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always @(D or WE)
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begin
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if (1'b1 == set) begin
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if (1'b1 == SET) begin
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data <= 1'b1;
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end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
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end else if ((1'b1 == D)&&(1'b1 == WE)) begin
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//----- Cases to program internal memory bit
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//----- case 1: bl = 1, wl = 1, a -> 0
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data <= 1'b1;
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end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
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end else if ((1'b0 == D)&&(1'b1 == WE)) begin
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//----- case 2: bl = 0, wl = 1, a -> 0
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data <= 1'b0;
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end
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@ -70,39 +75,83 @@ output outb // Data output
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`ifndef ENABLE_FORMAL_VERIFICATION
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// Wire q_reg to Q
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assign out = data;
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assign outb = ~data;
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assign Q = data;
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assign QN = ~data;
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`else
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assign out = 1'bZ;
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assign outb = !out;
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assign Q = 1'bZ;
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assign QN = !out;
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`endif
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endmodule
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module sram_blwl_set_reset(
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input reset, // Word line control signal
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input set, // Word line control signal
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input wl, // Word line control signal
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input bl, // Bit line control signal
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output out, // Data output
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output outb // Data output
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//-----------------------------------------------------
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// Function : A SRAM cell with
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// - an active-low set
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// - a write-enable
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//-----------------------------------------------------
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module SRAMSN(
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input SETN, // active-low set signal
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input WE, // Word line control signal as write enable
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input D, // Bit line control signal as data input
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output Q, // Data output
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output QN // Data output
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);
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//----- local variable need to be registered
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reg data;
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//----- when wl is enabled, we can read in data from bl
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always @(bl or wl)
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always @(D or WE)
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begin
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if (1'b1 == reset) begin
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if (1'b0 == SETN) begin
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data <= 1'b1;
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end else if ((1'b1 == D)&&(1'b1 == WE)) begin
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//----- Cases to program internal memory bit
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//----- case 1: bl = 1, wl = 1, a -> 0
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data <= 1'b1;
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end else if ((1'b0 == D)&&(1'b1 == WE)) begin
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//----- case 2: bl = 0, wl = 1, a -> 0
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data <= 1'b0;
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end
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end
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`ifndef ENABLE_FORMAL_VERIFICATION
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// Wire q_reg to Q
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assign Q = data;
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assign QN = ~data;
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`else
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assign Q = 1'bZ;
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assign QN = !out;
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`endif
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endmodule
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//-----------------------------------------------------
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// Function : A SRAM cell with
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// - an active-high reset
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// - a write-enable
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//-----------------------------------------------------
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module SRAMR(
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input RST, // active-high reset signal
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input WE, // Word line control signal as write enable
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input D, // Bit line control signal as data input
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output Q, // Data output
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output QN // Data output
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);
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//----- local variable need to be registered
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reg data;
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//----- when wl is enabled, we can read in data from bl
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always @(D or WE)
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begin
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if (1'b1 == RST) begin
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data <= 1'b0;
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end else if (1'b1 == set) begin
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data <= 1'b1;
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end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
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end else if ((1'b1 == D)&&(1'b1 == WE)) begin
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//----- Cases to program internal memory bit
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//----- case 1: bl = 1, wl = 1, a -> 0
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data <= 1'b1;
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end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
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end else if ((1'b0 == D)&&(1'b1 == WE)) begin
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//----- case 2: bl = 0, wl = 1, a -> 0
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data <= 1'b0;
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end
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@ -110,58 +159,150 @@ output outb // Data output
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`ifndef ENABLE_FORMAL_VERIFICATION
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// Wire q_reg to Q
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assign out = data;
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assign outb = ~data;
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assign Q = data;
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assign QN = ~data;
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`else
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assign out = 1'bZ;
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assign outb = !out;
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assign Q = 1'bZ;
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assign QN = !out;
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`endif
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endmodule
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//------ Module: sram6T_blwl -----//
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//------ Verilog file: sram.v -----//
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//------ Author: Xifan TANG -----//
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module sram6T_blwl(
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//input read,
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//input nequalize,
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input din, // Data input
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output dout, // Data output
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output doutb, // Data output
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input bl, // Bit line control signal
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input wl, // Word line control signal
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input blb // Inverted Bit line control signal
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//-----------------------------------------------------
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// Function : A SRAM cell with
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// - an active-low reset
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// - a write-enable
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//-----------------------------------------------------
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module SRAMRN(
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input RSTN, // active-low reset signal
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input WE, // Word line control signal as write enable
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input D, // Bit line control signal as data input
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output Q, // Data output
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output QN // Data output
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);
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//----- local variable need to be registered
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reg a;
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reg data;
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//----- when wl is enabled, we can read in data from bl
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always @(bl, wl)
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always @(D or WE)
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begin
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if (1'b0 == RSTN) begin
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data <= 1'b0;
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end else if ((1'b1 == D)&&(1'b1 == WE)) begin
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//----- Cases to program internal memory bit
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//----- case 1: bl = 1, wl = 1, a -> 0
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if ((1'b1 == bl)&&(1'b1 == wl)) begin
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a <= 1'b1;
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end
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data <= 1'b1;
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end else if ((1'b0 == D)&&(1'b1 == WE)) begin
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//----- case 2: bl = 0, wl = 1, a -> 0
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if ((1'b0 == bl)&&(1'b1 == wl)) begin
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a <= 1'b0;
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data <= 1'b0;
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end
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end
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// dout is short-wired to din
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assign dout = a;
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//---- doutb is always opposite to dout
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assign doutb = ~dout;
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`ifdef ENABLE_SIGNAL_INITIALIZATION
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initial begin
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$deposit(a, $random);
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end
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`ifndef ENABLE_FORMAL_VERIFICATION
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// Wire q_reg to Q
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assign Q = data;
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assign QN = ~data;
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`else
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assign Q = 1'bZ;
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assign QN = !out;
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`endif
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endmodule
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//-----------------------------------------------------
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// Function : A SRAM cell with
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// - an active-high reset
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// - an active-high set
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// - a write-enable
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//-----------------------------------------------------
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module SRAMSR(
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input RST, // active-high reset signal
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input SET, // active-high set signal
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input WE, // Word line control signal as write enable
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input D, // Bit line control signal as data input
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output Q, // Data output
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output QN // Data output
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);
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//----- local variable need to be registered
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reg data;
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//----- when wl is enabled, we can read in data from bl
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always @(D or WE)
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begin
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if (1'b1 == RST) begin
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data <= 1'b0;
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end else if (1'b1 == SET) begin
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data <= 1'b1;
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end else if ((1'b1 == D)&&(1'b1 == WE)) begin
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//----- Cases to program internal memory bit
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//----- case 1: bl = 1, wl = 1, a -> 0
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data <= 1'b1;
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end else if ((1'b0 == D)&&(1'b1 == WE)) begin
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//----- case 2: bl = 0, wl = 1, a -> 0
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data <= 1'b0;
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end
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end
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`ifndef ENABLE_FORMAL_VERIFICATION
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// Wire q_reg to Q
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assign Q = data;
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assign QN = ~data;
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`else
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assign Q = 1'bZ;
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assign QN = !out;
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`endif
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endmodule
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//-----------------------------------------------------
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// Function : A SRAM cell with
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// - an active-low reset
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// - an active-low set
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// - a write-enable
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//-----------------------------------------------------
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module SRAMSNRN(
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input RSTN, // active-low reset signal
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input SETN, // active-low set signal
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input WE, // Word line control signal as write enable
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input D, // Bit line control signal as data input
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output Q, // Data output
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output QN // Data output
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);
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//----- local variable need to be registered
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reg data;
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//----- when wl is enabled, we can read in data from bl
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always @(D or WE)
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begin
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if (1'b0 == RSTN) begin
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data <= 1'b0;
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end else if (1'b0 == SETN) begin
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data <= 1'b1;
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end else if ((1'b1 == D)&&(1'b1 == WE)) begin
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//----- Cases to program internal memory bit
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//----- case 1: bl = 1, wl = 1, a -> 0
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data <= 1'b1;
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end else if ((1'b0 == D)&&(1'b1 == WE)) begin
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//----- case 2: bl = 0, wl = 1, a -> 0
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data <= 1'b0;
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end
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end
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`ifndef ENABLE_FORMAL_VERIFICATION
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// Wire q_reg to Q
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assign Q = data;
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assign QN = ~data;
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`else
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assign Q = 1'bZ;
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assign QN = !out;
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`endif
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endmodule
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module sram6T_rram(
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input read,
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input nequalize,
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