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passing regression test on dpram benchmarks

This commit is contained in:
tangxifan 2019-11-07 14:57:46 -07:00
parent 56b4ee008e
commit d391983e8c
5 changed files with 326 additions and 51 deletions
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26
openfpga_flow/VerilogNetlists/dpram.v
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@ -1,20 +1,20 @@
//-----------------------------------------------------
// Design Name : dual_port_ram_32x1024
// File Name : dpram_32x1024.v
// Function : Dual port RAM 32x1024
// Design Name : dual_port_ram_32x512
// File Name : dpram.v
// Function : Dual port RAM 32x512
// Coder : Aurelien Alacchi
//-----------------------------------------------------
module dual_port_ram_32x1024 (
module dual_port_ram_32x512 (
input clk,
input wen,
input ren,
input[0:9] waddr,
input[0:9] raddr,
input[0:8] waddr,
input[0:8] raddr,
input[0:31] d_in,
output[0:31] d_out );
dual_port_sram_32x1024 memory_0 (
dual_port_sram_32x512 memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
@ -26,28 +26,28 @@ module dual_port_ram_32x1024 (
endmodule
module dual_port_sram_32x1024 (
module dual_port_sram_32x512 (
input wclk,
input wen,
input[0:9] waddr,
input[0:8] waddr,
input[0:31] data_in,
input rclk,
input ren,
input[0:9] raddr,
input[0:8] raddr,
output[0:31] d_out );
reg[0:31] ram[0:1023];
reg[0:31] ram[0:511];
reg[0:31] internal;
assign d_out = internal;
always @(negedge wclk) begin
always @(posedge wclk) begin
if(wen) begin
ram[waddr] <= data_in;
end
end
always @(negedge rclk) begin
always @(posedge rclk) begin
if(ren) begin
internal <= ram[raddr];
end

48
openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
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@ -146,7 +146,7 @@
<port name="Q"/>
</output_ports>
</model>
<model name="dual_port_ram_32x1024">
<model name="dual_port_ram_32x512">
<input_ports>
<port name="wen"/> <!-- control -->
<port name="ren"/> <!-- control -->
@ -421,16 +421,16 @@
<port type="output" prefix="sumout" size="1"/>
<port type="output" prefix="cout" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="dual_port_ram_32x1024" prefix="dual_port_ram_32x1024" dump_explicit_port_map="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/spram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram.v">
<circuit_model type="hard_logic" name="dual_port_ram_32x512" prefix="dual_port_ram_32x512" dump_explicit_port_map="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/spram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="buf1"/>
<output_buffer exist="on" circuit_model_name="buf1"/>
<port type="input" prefix="waddr" size="11"/>
<port type="input" prefix="raddr" size="11"/>
<port type="input" prefix="d_in" size="64"/>
<port type="input" prefix="waddr" size="9"/>
<port type="input" prefix="raddr" size="9"/>
<port type="input" prefix="d_in" size="32"/>
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="d_out" size="64"/>
<port type="output" prefix="d_out" size="32"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
@ -615,29 +615,29 @@
<pb_type name="memory_dp" height="2" area="548000">
<input name="waddr" num_pins="11" equivalent="false"/>
<input name="raddr" num_pins="11" equivalent="false"/>
<input name="d_in" num_pins="64" equivalent="false"/>
<input name="waddr" num_pins="9" equivalent="false"/>
<input name="raddr" num_pins="9" equivalent="false"/>
<input name="d_in" num_pins="32" equivalent="false"/>
<input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/>
<output name="d_out" num_pins="64" equivalent="false"/>
<output name="d_out" num_pins="32" equivalent="false"/>
<clock name="clk" num_pins="1"/>
<pb_type name="memory" num_pb="1">
<input name="waddr" num_pins="11"/>
<input name="raddr" num_pins="11"/>
<input name="d_in" num_pins="64"/>
<input name="waddr" num_pins="9"/>
<input name="raddr" num_pins="9"/>
<input name="d_in" num_pins="32"/>
<input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/>
<output name="d_out" num_pins="64"/>
<output name="d_out" num_pins="32"/>
<clock name="clk" num_pins="1"/>
<pb_type name="dpram" num_pb="1" blif_model=".subckt dual_port_ram_32x1024" circuit_model_name="dual_port_ram_32x1024">
<input name="waddr" num_pins="11" port_class="address"/>
<input name="raddr" num_pins="11" port_class="address"/>
<input name="d_in" num_pins="64" port_class="data_in"/>
<pb_type name="dpram" num_pb="1" blif_model=".subckt dual_port_ram_32x512" circuit_model_name="dual_port_ram_32x512">
<input name="waddr" num_pins="9" port_class="address"/>
<input name="raddr" num_pins="9" port_class="address"/>
<input name="d_in" num_pins="32" port_class="data_in"/>
<input name="wen" num_pins="1" port_class="write_en"/>
<input name="ren" num_pins="1" port_class="write_en"/>
<output name="d_out" num_pins="64" port_class="data_out"/>
<input name="ren" num_pins="1" port_class="read_en"/>
<output name="d_out" num_pins="32" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
@ -647,8 +647,8 @@
<direct name="address2" input="memory.raddr" output="dpram.raddr">
<delay_constant max="132e-12" in_port="memory.raddr" out_port="dpram.raddr"/>
</direct>
<direct name="data1" input="memory.d_in[63:0]" output="dpram.d_in">
<delay_constant max="132e-12" in_port="memory.d_in[63:0]" out_port="dpram.d_in"/>
<direct name="data1" input="memory.d_in[31:0]" output="dpram.d_in">
<delay_constant max="132e-12" in_port="memory.d_in[31:0]" out_port="dpram.d_in"/>
</direct>
<direct name="writeen1" input="memory.wen" output="dpram.wen">
<delay_constant max="132e-12" in_port="memory.wen" out_port="dpram.wen"/>
@ -656,8 +656,8 @@
<direct name="readen1" input="memory.ren" output="dpram.ren">
<delay_constant max="132e-12" in_port="memory.ren" out_port="dpram.ren"/>
</direct>
<direct name="dataout1" input="dpram.d_out" output="memory.d_out[63:0]">
<delay_constant max="40e-12" in_port="dpram.d_out" out_port="memory.d_out[63:0]"/>
<direct name="dataout1" input="dpram.d_out" output="memory.d_out[31:0]">
<delay_constant max="40e-12" in_port="dpram.d_out" out_port="memory.d_out[31:0]"/>
</direct>
<direct name="clk" input="memory.clk" output="dpram.clk">
</direct>

6
openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif
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@ -66,7 +66,7 @@
# End adder
# Start DPRAM
.subckt dual_port_ram_32x1024 clk=clk wen=wen_st1 ren=ren \
.subckt dual_port_ram_32x512 clk=clk wen=wen_st1 ren=ren \
waddr[0]=waddr_st1_0_ waddr[1]=waddr_st1_1_ waddr[2]=waddr_st1_2_ waddr[3]=waddr_st1_3_ waddr[4]=waddr_st1_4_ \
waddr[5]=waddr_st1_5_ waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 \
raddr[0]=raddr_0_ raddr[1]=raddr_1_ raddr[2]=raddr_2_ raddr[3]=raddr_3_ raddr[4]=raddr_4_ raddr[5]=raddr_5_ \
@ -94,8 +94,8 @@ d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=un
.end
# Start blackbox definition
.model dual_port_ram_32x1024
.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \
.model dual_port_ram_32x512
.inputs clk ren wen waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \
waddr[6] waddr[7] waddr[8] raddr[0] raddr[1] raddr[2] \
raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] \
d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \

30
openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v
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@ -1,9 +1,3 @@
// //
// ERI summit demo-benchmark //
// pipelined_8b_adder.v //
// by Aurelien //
// //
/////////////////////////////////////
//-----------------------------------------------------
// Design Name : pipelined_8bit_adder
// File Name : pipelined_8bit_adder.v
@ -57,11 +51,25 @@ module pipelined_8bit_adder(
output q_6_,
output q_7_);
wire [5:0] raddr = { raddr_5_, raddr_4_, raddr_3_, raddr_2_, raddr_1_, raddr_0_ };
wire [5:0] waddr = { waddr_5_, waddr_4_, waddr_3_, waddr_2_, waddr_1_, waddr_0_ };
wire [6:0] a = { a_6_, a_5_, a_4_, a_3_, a_2_, a_1_, a_0_ };
wire [6:0] b = { b_6_, b_5_, b_4_, b_3_, b_2_, b_1_, b_0_ };
wire [7:0] q = { q_7_, q_6_, q_5_, q_4_, q_3_, q_2_, q_1_, q_0_ };
wire [5:0] raddr;
wire [5:0] waddr;
wire [6:0] a;
wire [6:0] b;
wire [7:0] q;
assign raddr = { raddr_5_, raddr_4_, raddr_3_, raddr_2_, raddr_1_, raddr_0_ };
assign waddr = { waddr_5_, waddr_4_, waddr_3_, waddr_2_, waddr_1_, waddr_0_ };
assign a = { a_6_, a_5_, a_4_, a_3_, a_2_, a_1_, a_0_ };
assign b = { b_6_, b_5_, b_4_, b_3_, b_2_, b_1_, b_0_ };
assign q_7_ = q[7];
assign q_6_ = q[6];
assign q_5_ = q[5];
assign q_4_ = q[4];
assign q_3_ = q[3];
assign q_2_ = q[2];
assign q_1_ = q[1];
assign q_0_ = q[0];
reg[7:0] ram[63:0];
reg[6:0] a_st0;

267
openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder_formal_random_top_tb.v Normal file
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@ -0,0 +1,267 @@
//-----------------------------------------------------
// Design Name : pipelined_8bit_adder_top_formal_verification_random_tb
// File Name : pipelined_8bit_adder.v
// Function : Testbench for pipelined 8-bit adders, whose sum and carry outputs
// are cached in a dual-port memory.
// This testbench will do a verification of FPGA implementation
// of the pipelined 8-bit adders against the reference
// (original) Verilog netlist
// To provide a practical testing, this testbench will :
// - Instantiate a pre-programmed FPGA and the proper
// benchmark
// - Load memories with random values
// - Randomly write and read from the memories
// - Watch for any difference between FPGA and Benchmark
// outputs, after memories are fully loaded
//
// PLEASE USE this testbench instead of the auto-generated test
// benches when performing verification!
// Coder : Aurelien Alacchi and Xifan Tang
//-----------------------------------------------------
`timescale 1 ns/ 100 ps
module pipelined_8bit_adder_top_formal_verification_random_tb();
reg clk;
reg[5:0] raddr;
reg[5:0] waddr;
reg ren;
reg wen;
reg[6:0] a;
reg[6:0] b;
wire[7:0] q_gfpga;
wire[7:0] q_bench;
reg[7:0] q_flag;
pipelined_8bit_adder_top_formal_verification DUT(
.clk_fm (clk),
.ren_fm (ren),
.wen_fm (wen),
.raddr_0__fm (raddr[0]),
.raddr_1__fm (raddr[1]),
.raddr_2__fm (raddr[2]),
.raddr_3__fm (raddr[3]),
.raddr_4__fm (raddr[4]),
.raddr_5__fm (raddr[5]),
.waddr_0__fm (waddr[0]),
.waddr_1__fm (waddr[1]),
.waddr_2__fm (waddr[2]),
.waddr_3__fm (waddr[3]),
.waddr_4__fm (waddr[4]),
.waddr_5__fm (waddr[5]),
.a_0__fm (a[0]),
.a_1__fm (a[1]),
.a_2__fm (a[2]),
.a_3__fm (a[3]),
.a_4__fm (a[4]),
.a_5__fm (a[5]),
.a_6__fm (a[6]),
.b_0__fm (b[0]),
.b_1__fm (b[1]),
.b_2__fm (b[2]),
.b_3__fm (b[3]),
.b_4__fm (b[4]),
.b_5__fm (b[5]),
.b_6__fm (b[6]),
.out_q_0__fm (q_gfpga[0]),
.out_q_1__fm (q_gfpga[1]),
.out_q_2__fm (q_gfpga[2]),
.out_q_3__fm (q_gfpga[3]),
.out_q_4__fm (q_gfpga[4]),
.out_q_5__fm (q_gfpga[5]),
.out_q_6__fm (q_gfpga[6]),
.out_q_7__fm (q_gfpga[7])
);
pipelined_8bit_adder ref0(
.clk (clk),
.ren (ren),
.wen (wen),
.raddr_0_ (raddr[0]),
.raddr_1_ (raddr[1]),
.raddr_2_ (raddr[2]),
.raddr_3_ (raddr[3]),
.raddr_4_ (raddr[4]),
.raddr_5_ (raddr[5]),
.waddr_0_ (waddr[0]),
.waddr_1_ (waddr[1]),
.waddr_2_ (waddr[2]),
.waddr_3_ (waddr[3]),
.waddr_4_ (waddr[4]),
.waddr_5_ (waddr[5]),
.a_0_ (a[0]),
.a_1_ (a[1]),
.a_2_ (a[2]),
.a_3_ (a[3]),
.a_4_ (a[4]),
.a_5_ (a[5]),
.a_6_ (a[6]),
.b_0_ (b[0]),
.b_1_ (b[1]),
.b_2_ (b[2]),
.b_3_ (b[3]),
.b_4_ (b[4]),
.b_5_ (b[5]),
.b_6_ (b[6]),
.q_0_ (q_bench[0]),
.q_1_ (q_bench[1]),
.q_2_ (q_bench[2]),
.q_3_ (q_bench[3]),
.q_4_ (q_bench[4]),
.q_5_ (q_bench[5]),
.q_6_ (q_bench[6]),
.q_7_ (q_bench[7])
);
integer nb_error = 0;
integer count = 0;
integer lim_max = 64 - 1;
integer write_complete = 0;
//----- Initialization
initial begin
clk <= 1'b0;
a <= 7'h00;
b <= 7'h00;
wen <= 1'b0;
ren <= 1'b0;
waddr <= 6'h00;
raddr <= 6'h00;
while(1) begin
#2.5
clk <= !clk;
end
end
//----- Input Stimulis
always@(negedge clk) begin
if(write_complete == 0) begin
wen <= 1'b1;
ren <= 1'b0;
count <= count + 1;
waddr <= waddr + 1;
if(count == lim_max) begin
write_complete = 1;
end
end else begin
wen <= $random;
ren <= $random;
waddr <= $random;
raddr <= $random;
end
a <= $random;
b <= $random;
end
always@(negedge clk) begin
if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin
q_flag[0] <= 1'b1;
end else begin
q_flag[0] <= 1'b0;
end
if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin
q_flag[1] <= 1'b1;
end else begin
q_flag[1] <= 1'b0;
end
if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin
q_flag[2] <= 1'b1;
end else begin
q_flag[2] <= 1'b0;
end
if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin
q_flag[3] <= 1'b1;
end else begin
q_flag[3] <= 1'b0;
end
if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin
q_flag[4] <= 1'b1;
end else begin
q_flag[4] <= 1'b0;
end
if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin
q_flag[5] <= 1'b1;
end else begin
q_flag[5] <= 1'b0;
end
if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin
q_flag[6] <= 1'b1;
end else begin
q_flag[6] <= 1'b0;
end
if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin
q_flag[7] <= 1'b1;
end else begin
q_flag[7] <= 1'b0;
end
end
always@(posedge q_flag[0]) begin
if(q_flag[0]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[0] at time = %t", $realtime);
end
end
always@(posedge q_flag[1]) begin
if(q_flag[1]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[1] at time = %t", $realtime);
end
end
always@(posedge q_flag[2]) begin
if(q_flag[2]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[2] at time = %t", $realtime);
end
end
always@(posedge q_flag[3]) begin
if(q_flag[3]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[3] at time = %t", $realtime);
end
end
always@(posedge q_flag[4]) begin
if(q_flag[4]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[4] at time = %t", $realtime);
end
end
always@(posedge q_flag[5]) begin
if(q_flag[5]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[5] at time = %t", $realtime);
end
end
always@(posedge q_flag[6]) begin
if(q_flag[6]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[6] at time = %t", $realtime);
end
end
always@(posedge q_flag[7]) begin
if(q_flag[7]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[7] at time = %t", $realtime);
end
end
initial begin
$dumpfile("pipelined_8bit_adder_formal.vcd");
$dumpvars(1, pipelined_8bit_adder_top_formal_verification_random_tb);
end
initial begin
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
#1500 // Can be changed by the user for his need
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule