[Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA
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@ -196,7 +196,7 @@
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<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
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<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="DFFRQ" default_val="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/sky130_fd_sc_hd_wrapper.v">
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<circuit_model type="hard_logic" name="CARRY_MUX2" prefix="CARRY_MUX2" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/mux2.v">
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<design_technology type="cmos"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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@ -204,7 +204,7 @@
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<port type="input" prefix="a" lib_name="A0" size="1"/>
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<port type="input" prefix="b" lib_name="A1" size="1"/>
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<port type="input" prefix="cin" lib_name="S" size="1"/>
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<port type="output" prefix="cout" lib_name="X" size="1"/>
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<port type="output" prefix="cout" lib_name="Y" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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@ -249,7 +249,7 @@
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="sky130_fd_sc_hd__mux2_1_wrapper"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="CARRY_MUX2"/>
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<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="SDFFRQ"/>
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<!-- Binding operating pb_type to physical pb_type -->
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<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
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