[Test] Add example XML for net mapping between benchmark to FPGA

openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/fpga_port_nets.xml

@@ -0,0 +1,9 @@
+<fpga_port_nets>
+  <!-- For a given .blif file, we want to assign 
+       - the clk0 signal to the clk[0] port of the FPGA fabric
+       - the clk1 signal to the clk[1] port of the FPGA fabric
+    -->
+  <port net="clk0" fpga="clk[0]"/>
+  <port net="clk1" fpga="clk[1]"/>
+</fpga_port_nets>
+