From ab25e1af5f2e913e4c83946d5fbdfa8a5fb84b6e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 19 Jan 2021 09:29:21 -0700
Subject: [PATCH] [Test] Add example XML for net mapping between benchmark to
 FPGA

---
 .../global_tile_4clock/config/fpga_port_nets.xml         | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/fpga_port_nets.xml

diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/fpga_port_nets.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/fpga_port_nets.xml
new file mode 100644
index 000000000..5b8ec18d3
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/fpga_port_nets.xml
@@ -0,0 +1,9 @@
+<fpga_port_nets>
+  <!-- For a given .blif file, we want to assign 
+       - the clk0 signal to the clk[0] port of the FPGA fabric
+       - the clk1 signal to the clk[1] port of the FPGA fabric
+    -->
+  <port net="clk0" fpga="clk[0]"/>
+  <port net="clk1" fpga="clk[1]"/>
+</fpga_port_nets>
+