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[Test] Update regression test cases for fpga verilog

This commit is contained in:
tangxifan 2021-02-28 12:24:36 -07:00
parent ff29cc3dff
commit 27200e3daa
1 changed files with 3 additions and 3 deletions
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6
openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -93,13 +93,13 @@ echo -e "Testing Verilog generation with routing multiplexers without constant i
run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
echo -e "Testing Verilog generation with behavioral description";
run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs
run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog --debug --show_thread_logs
echo -e "Testing synthesizable Verilog generation with external standard cells";
run-task fpga_verilog/synthesizable_verilog --debug --show_thread_logs
run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --show_thread_logs
echo -e "Testing implicit Verilog generation";
run-task fpga_verilog/implicit_verilog --debug --show_thread_logs
run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs
echo -e "Testing Verilog generation with flatten routing modules";
run-task fpga_verilog/flatten_routing --debug --show_thread_logs