From 27200e3daaaacd0827e52855075c9f8a6d921af1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 28 Feb 2021 12:24:36 -0700 Subject: [PATCH] [Test] Update regression test cases for fpga verilog --- .../regression_test_scripts/fpga_verilog_reg_test.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 3d7db9b0c..acdf9a446 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -93,13 +93,13 @@ echo -e "Testing Verilog generation with routing multiplexers without constant i run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs echo -e "Testing Verilog generation with behavioral description"; -run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs +run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog --debug --show_thread_logs echo -e "Testing synthesizable Verilog generation with external standard cells"; -run-task fpga_verilog/synthesizable_verilog --debug --show_thread_logs +run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --show_thread_logs echo -e "Testing implicit Verilog generation"; -run-task fpga_verilog/implicit_verilog --debug --show_thread_logs +run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs echo -e "Testing Verilog generation with flatten routing modules"; run-task fpga_verilog/flatten_routing --debug --show_thread_logs