[Script] Patch the yosys rewrite script to avoid existing blif outputs

openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys

@@ -19,12 +19,12 @@ synth -run check
 
 # Clean and output blif
 opt_clean -purge
-write_blif ${OUTPUT_BLIF}
+write_blif rewritten_${OUTPUT_BLIF}
 
 # Clear all the designs
 design -reset
 
 # Rewrite the .blif to Verilog
 # so that the pin sequence matches
-read_blif ${OUTPUT_BLIF}
+read_blif rewritten_${OUTPUT_BLIF}
 write_verilog ${OUTPUT_VERILOG}