diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
index 6da1a7987..b3faf9605 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
@@ -19,12 +19,12 @@ synth -run check
 
 # Clean and output blif
 opt_clean -purge
-write_blif ${OUTPUT_BLIF}
+write_blif rewritten_${OUTPUT_BLIF}
 
 # Clear all the designs
 design -reset
 
 # Rewrite the .blif to Verilog
 # so that the pin sequence matches
-read_blif ${OUTPUT_BLIF}
+read_blif rewritten_${OUTPUT_BLIF}
 write_verilog ${OUTPUT_VERILOG}