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[Arch] Bug fix due to valid default value parser

This commit is contained in:
tangxifan 2020-12-02 17:51:50 -07:00
parent 8350b0f911
commit 412fb5bb31
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -218,7 +218,7 @@
</direct_connection>
<tile_annotations>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
<global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
<global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="0"/>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->