[Doc] Update documentation about default value definition in tile annotation

docs/source/manual/arch_lang/annotate_vpr_arch.rst

@@ -60,7 +60,7 @@ Here is an example:
 .. code-block:: xml
 
   <tile_annotations>
-    <global_port name="<string>" tile_port="<string>" is_clock="<bool>" is_reset="<bool>" is_set="<bool>"/>
+    <global_port name="<string>" tile_port="<string>" is_clock="<bool>" is_reset="<bool>" is_set="<bool>" default_val="<int>"/>
   </tile_annotations>
 
 - ``name="<string>"`` is the port name to appear in the top-level FPGA fabric.
@@ -85,6 +85,8 @@ Here is an example:
 
 .. note:: All the global port from a physical tile port is only used in operating phase. Any ports for programmable use are not allowed!
 
+- ``default_val="<int>"`` define if the default value for the global port when initialized in testbenches. Valid values are either ``0`` or ``1``. For example, the default value of an active-high reset pin is ``0``, while an active-low reset pin is ``1``.
+
 A more illustrative example:
 
 :numref:`fig_global_tile_ports` illustrates the difference between the global ports defined through ``circuit_model`` and ``tile_annotation``.