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[Flow] Update the design constraint file to follow bug fix in parser

This commit is contained in:
tangxifan 2021-01-17 10:41:01 -07:00
parent 113119bd8e
commit ea9d6bfe91
2 changed files with 4 additions and 4 deletions
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4
libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml
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@ -1,7 +1,7 @@
<repack_pin_constraints>
<repack_design_constraints>
<pin_constraint pb_type="clb" pin="clk[0]" net="clk0"/>
<pin_constraint pb_type="clb" pin="clk[1]" net="clk1"/>
<pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/>
<pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
</repack_pin_constraints>
</repack_design_constraints>

4
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml
View File

@ -1,4 +1,4 @@
<repack_pin_constraints>
<repack_design_constraints>
<!-- For a given .blif file, we want to assign
- the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
- the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
@ -10,5 +10,5 @@
<pin_constraint pb_type="clb" pin="clk[1]" net="clk1"/>
<pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/>
<pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
</repack_pin_constraints>
</repack_design_constraints>