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Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS

This commit is contained in:
Lalit Sharma 2021-03-07 22:01:35 -08:00
parent 2b2acae757
commit 6a1ce01084
3 changed files with 2 additions and 12 deletions
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2
openfpga_flow/misc/qlf_yosys.ys
View File

@ -2,6 +2,6 @@
# Read verilog files
${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE}
synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
write_verilog -noattr -nohex ${TOP_MODULE}.v

10
openfpga_flow/scripts/run_fpga_flow.py
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@ -494,16 +494,6 @@ def run_yosys_with_abc():
tmpVar = OpenFPGAArgs[indx][2:].upper()
ys_params[tmpVar] = OpenFPGAArgs[indx+1]
if 'YOSYS_FAMILY' not in ys_params.keys():
# define default family as 'qlf_k4n8'
ys_params['YOSYS_FAMILY'] = "qlf_k4n8"
# prefix value of YOSYS_MODE with '-' as an option in yosys script
if 'YOSYS_MODE' in ys_params.keys():
ys_params['YOSYS_MODE'] = "-" + ys_params['YOSYS_MODE']
else:
ys_params['YOSYS_MODE'] = ""
yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
tmpl = Template(open(yosys_template, encoding='utf-8').read())

2
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
View File

@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_circuit_format=eblif
yosys_mode = no_adder
yosys_args = -no_adder -family qlf_k4n8
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml