diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys
index 638103885..c90b8c5ac 100644
--- a/openfpga_flow/misc/qlf_yosys.ys
+++ b/openfpga_flow/misc/qlf_yosys.ys
@@ -2,6 +2,6 @@
 # Read verilog files
 ${READ_VERILOG_FILE}
 
-synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE}
+synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
 
 write_verilog -noattr -nohex ${TOP_MODULE}.v
\ No newline at end of file
diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index bddda8d15..e91d34a78 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -494,16 +494,6 @@ def run_yosys_with_abc():
         tmpVar = OpenFPGAArgs[indx][2:].upper()
         ys_params[tmpVar] = OpenFPGAArgs[indx+1]
     
-    if 'YOSYS_FAMILY' not in ys_params.keys():
-        # define default family as 'qlf_k4n8'
-        ys_params['YOSYS_FAMILY'] = "qlf_k4n8"
-
-    # prefix value of YOSYS_MODE with '-' as an option in yosys script
-    if 'YOSYS_MODE' in ys_params.keys():
-        ys_params['YOSYS_MODE'] = "-" + ys_params['YOSYS_MODE']
-    else:
-        ys_params['YOSYS_MODE'] = ""
-
     yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
         cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
     tmpl = Template(open(yosys_template, encoding='utf-8').read())
diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
index eba623ee8..824d92301 100644
--- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
@@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_vpr_circuit_format=eblif
-yosys_mode = no_adder
+yosys_args = -no_adder -family qlf_k4n8
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml