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bug fixed for frame-based configuration memory in top-level full testbench

This commit is contained in:
tangxifan 2020-05-28 18:22:27 -06:00
parent f5968fda52
commit 6a72c66eb8
3 changed files with 10 additions and 4 deletions
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5
openfpga/src/fpga_verilog/verilog_decoders.cpp
View File

@ -299,7 +299,12 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
* data_inv = ~data_inv
*/
if (1 == data_size) {
fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ") begin" << std::endl;
fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
fp << "\t";
print_verilog_wire_connection(fp, data_port, addr_port, false);
fp << "\t" << "end" << std::endl;
fp << "end" << std::endl;
/* Depend on if the inverted data output port is needed or not */
if (true == decoder_lib.use_data_inv_port(decoder)) {

3
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -102,7 +102,7 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp,
ModulePortId din_port_id = module_manager.find_module_port(top_module,
std::string(DECODER_DATA_IN_PORT_NAME));
BasicPort din_port = module_manager.module_port(top_module, din_port_id);
fp << generate_verilog_port(VERILOG_PORT_WIRE, din_port) << ";" << std::endl;
fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl;
/* Wire the programming clock to the enable signal */
print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to programming clock -----"));
@ -111,6 +111,7 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp,
BasicPort en_port = module_manager.module_port(top_module, en_port_id);
BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl;
print_verilog_wire_connection(fp, en_port, prog_clock_port, false);
}

6
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
View File

@ -142,7 +142,7 @@
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_mem" prefix="config_mem" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
@ -158,13 +158,13 @@
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_mem" default_val="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="frame_based" circuit_model_name="config_mem"/>
<organization type="frame_based" circuit_model_name="config_latch"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>