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bug fixed in k6_n10_40 architecture

This commit is contained in:
tangxifan 2020-05-31 18:58:44 -06:00
parent 0b9971cb5c
commit f73dfa2bcc
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
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@ -54,7 +54,7 @@
<site pb_type="clb"/>
</equivalent_sites>
<input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="10" equivalent="instance"/>
<output name="O" num_pins="10" equivalent="none"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
@ -197,7 +197,7 @@
-->
<pb_type name="clb">
<input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="10" equivalent="instance"/>
<output name="O" num_pins="10" equivalent="none"/>
<clock name="clk" num_pins="1"/>
<!-- Describe basic logic element.
Each basic logic element has a 6-LUT that can be optionally registered