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[Test] Use counter4bit in the multi-clock test

This commit is contained in:
tangxifan 2021-01-13 13:34:59 -07:00
parent ccf3e037ff
commit 91f12071d5
3 changed files with 6 additions and 75 deletions
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29
openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
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@ -1,29 +0,0 @@
module counter_2clock(clk0, q0, rst0, clk1, q1, rst1);
input clk0;
input rst0;
output [7:0] q0;
reg [7:0] q0;
input clk1;
input rst1;
output [7:0] q1;
reg [7:0] q1;
always @ (posedge clk0)
begin
if(rst0)
q0 <= 8'b00000000;
else
q0 <= q0 + 1;
end
always @ (posedge clk1)
begin
if(rst1)
q1 <= 8'b00000000;
else
q1 <= q1 + 1;
end
endmodule

42
openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock_tb.v
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@ -1,42 +0,0 @@
module counter_2clock_tb;
reg clk0, rst0;
wire [7:0] q0;
reg clk1, rst1;
wire [7:0] q1;
counter_2clock C_1(
clk0,
q0,
rst0);
counter_2clock C_1(
clk1,
q1,
rst1);
initial begin
#0 rst0 = 1'b1; clk0 = 1'b0;
#100 rst0 = 1'b0;
end
always begin
#10 clk0 = ~clk0;
end
initial begin
#0 rst1 = 1'b1; clk1 = 1'b0;
#100 rst1 = 1'b0;
end
always begin
#20 clk1 = ~clk1;
end
initial begin
#5000 $stop;
end
endmodule

10
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf
View File

@ -19,6 +19,7 @@ timeout_each_job = 20*60
# based on yosys outputs with correct clock assignment!
# TODO: This limitation should be removed and we should use yosys_vpr flow!!!
fpga_flow=vpr_blif
#fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
@ -29,12 +30,13 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.blif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v
[SYNTHESIS_PARAM]
bench0_top = counter_2clock
bench0_act=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.act
bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
bench0_top = counter4bit_2clock
bench0_act=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act
bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]