From 91f12071d50571d4ed96334b198219be51f3ce49 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 13 Jan 2021 13:34:59 -0700
Subject: [PATCH] [Test] Use counter4bit in the multi-clock test

---
 .../counter_2clock/counter_2clock.v           | 29 -------------
 .../counter_2clock/counter_2clock_tb.v        | 42 -------------------
 .../global_tile_4clock/config/task.conf       | 10 +++--
 3 files changed, 6 insertions(+), 75 deletions(-)
 delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
 delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock_tb.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
deleted file mode 100644
index 428392581..000000000
--- a/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
+++ /dev/null
@@ -1,29 +0,0 @@
-module counter_2clock(clk0, q0, rst0, clk1, q1, rst1);
-
-    input clk0;
-    input rst0;
-    output [7:0] q0;
-    reg [7:0] q0;
-
-    input clk1;
-    input rst1;
-    output [7:0] q1;
-    reg [7:0] q1;
-
-    always @ (posedge clk0)
-    begin
-        if(rst0)
-		q0 <= 8'b00000000;
-	else
-		q0 <= q0 + 1;
-    end
-
-    always @ (posedge clk1)
-    begin
-        if(rst1)
-		q1 <= 8'b00000000;
-	else
-		q1 <= q1 + 1;
-    end
-
-endmodule
diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock_tb.v
deleted file mode 100644
index d1957dc99..000000000
--- a/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock_tb.v
+++ /dev/null
@@ -1,42 +0,0 @@
-module counter_2clock_tb;
-
-	reg clk0, rst0;
-	wire [7:0] q0;
-
-	reg clk1, rst1;
-	wire [7:0] q1;
-
-	counter_2clock C_1(
-		clk0, 
-		q0, 
-		rst0);
-
-	counter_2clock C_1(
-		clk1, 
-		q1, 
-		rst1);
-	
-	initial begin
-		#0 rst0 = 1'b1; clk0 = 1'b0;
-		#100 rst0 = 1'b0;
-	end
-
-	always begin
-		#10 clk0 = ~clk0;
-	end
-
-	initial begin
-		#0 rst1 = 1'b1; clk1 = 1'b0;
-		#100 rst1 = 1'b0;
-	end
-
-	always begin
-		#20 clk1 = ~clk1;
-	end
-
-	
-	initial begin
-		#5000 $stop;
-	end
-
-endmodule
diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf
index a1f3f6b1d..99c5bd480 100644
--- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf
@@ -19,6 +19,7 @@ timeout_each_job = 20*60
 # based on yosys outputs with correct clock assignment!
 # TODO: This limitation should be removed and we should use yosys_vpr flow!!!
 fpga_flow=vpr_blif
+#fpga_flow=yosys_vpr
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
@@ -29,12 +30,13 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif
+#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v
 
 [SYNTHESIS_PARAM]
-bench0_top = counter_2clock
-bench0_act=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.act
-bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
+bench0_top = counter4bit_2clock
+bench0_act=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act
+bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]