[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'

openfpga_flow/misc/ys_tmpl_rewrite_flow.ys

@@ -0,0 +1,4 @@
+# Rewrite the .blif to Verilog
+# so that the pin sequence matches
+read_blif rewritten_${OUTPUT_BLIF}
+write_verilog ${OUTPUT_VERILOG}

openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys

@@ -20,11 +20,3 @@ synth -run check
 # Clean and output blif
 opt_clean -purge
 write_blif rewritten_${OUTPUT_BLIF}
-
-# Clear all the designs
-design -reset
-
-# Rewrite the .blif to Verilog
-# so that the pin sequence matches
-read_blif rewritten_${OUTPUT_BLIF}
-write_verilog ${OUTPUT_VERILOG}