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[Test] Use custom rewriting script in lut_adder test

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tangxifan 2021-03-10 13:48:20 -07:00
parent 0e772bc3b4
commit d21909ad6c
1 changed files with 1 additions and 0 deletions
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openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
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@ -31,6 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad
[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
bench1_top = adder_8