[HDL] Bug fix in the GP output pad

2020-11-02 18:37:53 -07:00 · 2020-11-02 18:37:53 -07:00 · c036c87d6d
parent 1e47203c7c
commit c036c87d6d
1 changed files with 3 additions and 3 deletions
--- a/openfpga_flow/openfpga_cell_library/verilog/gpio.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/gpio.v
@ -33,8 +33,8 @@ endmodule
 // Function    : A minimum output pad
 //-----------------------------------------------------
 module GPOUT (
-  inout A, // External PAD signal
-  input Y // Data output
+  inout Y, // External PAD signal
+  input A // Data output
 );
-  assign A = Y;
+  assign Y = A;
 endmodule