Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
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@ -2,5 +2,5 @@
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# Read verilog files
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${READ_VERILOG_FILE}
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synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -no_adder -top ${TOP_MODULE}
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synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE}
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@ -99,6 +99,10 @@ parser.add_argument('--arch_variable_file', type=str, default=None,
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# help="Key file for shell")
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parser.add_argument('--yosys_tmpl', type=str, default=None,
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help="Alternate yosys template, generates top_module.blif")
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parser.add_argument('--yosys_mode', type=str, default=None,
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help="Specify adder/no_adder mode for yosys run. Default is adder")
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parser.add_argument('--yosys_family', type=str, default="qlf_k4n8",
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help="Specify device family for yosys run")
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parser.add_argument('--disp', action="store_true",
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help="Open display while running VPR")
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parser.add_argument('--debug', action="store_true",
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@ -480,6 +484,16 @@ def run_yosys_with_abc():
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logger.exception("Failed to extract lut_size from XML file")
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clean_up_and_exit("")
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args.K = lut_size
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YS_MODE=""
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# Yosys valid mode option is "no_adder".
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if args.yosys_mode is not None:
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if args.yosys_mode.lower() == "no_adder":
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YS_MODE = "-" + args.yosys_mode
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else:
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logger.warning("Invalid value '" + args.yosys_mode + "' specified for synthesis_param 'bench_yosys_mode'")
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logger.warning("Considering default yosys mode i.e. adder mode")
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# Yosys script parameter mapping
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ys_params = {
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"READ_VERILOG_FILE": " \n".join([
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@ -488,6 +502,8 @@ def run_yosys_with_abc():
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"TOP_MODULE": args.top_module,
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"LUT_SIZE": lut_size,
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"OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
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"YOSYS_FAMILY": args.yosys_family,
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"YOSYS_MODE": YS_MODE,
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}
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yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
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cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
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@ -255,6 +255,8 @@ def generate_each_task_actions(taskname):
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# Read provided benchmark configurations
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# Common configurations
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ys_for_task_common = SynthSection.get("bench_yosys_common")
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ys_yosys_mode = SynthSection.get("bench_yosys_mode")
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ys_yosys_family = SynthSection.get("bench_yosys_family")
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chan_width_common = SynthSection.get("bench_chan_width_common")
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# Individual benchmark configuration
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@ -263,6 +265,10 @@ def generate_each_task_actions(taskname):
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fallback="top")
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CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys",
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fallback=ys_for_task_common)
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CurrBenchPara["yosys_mode"] = SynthSection.get(bech_name+"_yosys_mode",
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fallback=ys_yosys_mode)
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CurrBenchPara["yosys_family"] = SynthSection.get(bech_name+"_yosys_family",
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fallback=ys_yosys_family)
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CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
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fallback=chan_width_common)
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@ -381,6 +387,12 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
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if benchmark_obj.get("ys_script"):
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command += ["--yosys_tmpl", benchmark_obj["ys_script"]]
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if benchmark_obj.get("yosys_mode"):
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command += ["--yosys_mode", benchmark_obj["yosys_mode"]]
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if benchmark_obj.get("yosys_family"):
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command += ["--yosys_family", benchmark_obj["yosys_family"]]
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if task_gc.getboolean("power_analysis"):
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command += ["--power"]
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command += ["--power_tech", task_gc.get("power_tech_file")]
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@ -48,40 +48,27 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_en
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#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
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[SYNTHESIS_PARAM]
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bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench_yosys_mode=no_adder
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bench_yosys_family=qlf_k4n8
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bench0_top = io_tc1
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bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench1_top = unsigned_mult_80
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bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench2_top = bin2bcd
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bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench3_top = counter
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bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench5_top = rs_decoder_top
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bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench6_top = top_module
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bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench7_top = sha256
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bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench8_top = cavlc_top
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bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench9_top = cf_fft_256_8
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bench9_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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#bench10_top = counter120bitx5
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#bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench11_top = top
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bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench12_top = dct_mac
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bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench13_top = des_perf
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bench13_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench14_top = diffeq_f_systemC
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bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench15_top = i2c_master_top
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bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench16_top = iir
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bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench17_top = jpeg_qnr
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bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench18_top = multi_enc_decx2x4
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# sdc_controller requires 4 clocks
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#bench19_top = sdc_controller
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