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Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables

This commit is contained in:
Lalit Sharma 2021-03-01 22:31:15 -08:00
parent a162ee0661
commit 817729ac86
4 changed files with 32 additions and 17 deletions
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2
openfpga_flow/misc/qlf_yosys.ys
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@ -2,5 +2,5 @@
# Read verilog files
${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -no_adder -top ${TOP_MODULE}
synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE}

16
openfpga_flow/scripts/run_fpga_flow.py
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@ -99,6 +99,10 @@ parser.add_argument('--arch_variable_file', type=str, default=None,
# help="Key file for shell")
parser.add_argument('--yosys_tmpl', type=str, default=None,
help="Alternate yosys template, generates top_module.blif")
parser.add_argument('--yosys_mode', type=str, default=None,
help="Specify adder/no_adder mode for yosys run. Default is adder")
parser.add_argument('--yosys_family', type=str, default="qlf_k4n8",
help="Specify device family for yosys run")
parser.add_argument('--disp', action="store_true",
help="Open display while running VPR")
parser.add_argument('--debug', action="store_true",
@ -480,6 +484,16 @@ def run_yosys_with_abc():
logger.exception("Failed to extract lut_size from XML file")
clean_up_and_exit("")
args.K = lut_size
YS_MODE=""
# Yosys valid mode option is "no_adder".
if args.yosys_mode is not None:
if args.yosys_mode.lower() == "no_adder":
YS_MODE = "-" + args.yosys_mode
else:
logger.warning("Invalid value '" + args.yosys_mode + "' specified for synthesis_param 'bench_yosys_mode'")
logger.warning("Considering default yosys mode i.e. adder mode")
# Yosys script parameter mapping
ys_params = {
"READ_VERILOG_FILE": " \n".join([
@ -488,6 +502,8 @@ def run_yosys_with_abc():
"TOP_MODULE": args.top_module,
"LUT_SIZE": lut_size,
"OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
"YOSYS_FAMILY": args.yosys_family,
"YOSYS_MODE": YS_MODE,
}
yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")

12
openfpga_flow/scripts/run_fpga_task.py
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@ -255,6 +255,8 @@ def generate_each_task_actions(taskname):
# Read provided benchmark configurations
# Common configurations
ys_for_task_common = SynthSection.get("bench_yosys_common")
ys_yosys_mode = SynthSection.get("bench_yosys_mode")
ys_yosys_family = SynthSection.get("bench_yosys_family")
chan_width_common = SynthSection.get("bench_chan_width_common")
# Individual benchmark configuration
@ -263,6 +265,10 @@ def generate_each_task_actions(taskname):
fallback="top")
CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys",
fallback=ys_for_task_common)
CurrBenchPara["yosys_mode"] = SynthSection.get(bech_name+"_yosys_mode",
fallback=ys_yosys_mode)
CurrBenchPara["yosys_family"] = SynthSection.get(bech_name+"_yosys_family",
fallback=ys_yosys_family)
CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
fallback=chan_width_common)
@ -381,6 +387,12 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
if benchmark_obj.get("ys_script"):
command += ["--yosys_tmpl", benchmark_obj["ys_script"]]
if benchmark_obj.get("yosys_mode"):
command += ["--yosys_mode", benchmark_obj["yosys_mode"]]
if benchmark_obj.get("yosys_family"):
command += ["--yosys_family", benchmark_obj["yosys_family"]]
if task_gc.getboolean("power_analysis"):
command += ["--power"]
command += ["--power_tech", task_gc.get("power_tech_file")]

19
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
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@ -48,40 +48,27 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_en
#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench_yosys_mode=no_adder
bench_yosys_family=qlf_k4n8
bench0_top = io_tc1
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench1_top = unsigned_mult_80
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench2_top = bin2bcd
bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench3_top = counter
bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench5_top = rs_decoder_top
bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench6_top = top_module
bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench7_top = sha256
bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench8_top = cavlc_top
bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench9_top = cf_fft_256_8
bench9_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
#bench10_top = counter120bitx5
#bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench11_top = top
bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench12_top = dct_mac
bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench13_top = des_perf
bench13_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench14_top = diffeq_f_systemC
bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench15_top = i2c_master_top
bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench16_top = iir
bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench17_top = jpeg_qnr
bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench18_top = multi_enc_decx2x4
# sdc_controller requires 4 clocks
#bench19_top = sdc_controller