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[Test] bug fix in test case

This commit is contained in:
tangxifan 2021-02-18 18:56:40 -07:00
parent affc8cbbc4
commit e19fc15fec
1 changed files with 3 additions and 3 deletions
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6
openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf
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@ -27,11 +27,11 @@ openfpga_vpr_device_layout=auto
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmarks/FIR_filter/FIR_filter_firBlock_left_debug.blif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/FIR_filter/FIR_filter_firBlock_left_debug.blif
[SYNTHESIS_PARAM]
bench0_top=FIR_filter_firBlock_left
bench0_act=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmarks/FIR_filter/FIR_filter_firBlock_left_ace_out_debug.act
bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmarks/FIR_filter/FIR_filter_firBlock_left_output_verilog_debug.v
bench0_act=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/FIR_filter/FIR_filter_firBlock_left_ace_out_debug.act
bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/FIR_filter/FIR_filter_firBlock_left_output_verilog_debug.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]